PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 208

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PSB21473FV13XT

Manufacturer Part Number
PSB21473FV13XT
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB21473FV13XT

Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Lead Free Status / RoHS Status
Compliant
INCA-D
PSB 21473
General Purpose Timer Unit
Timer 6 in Gated Timer Mode
Gated timer mode for the core timer T6 is selected by setting bit field T6M in register
T6CON to ‘010
’ or ‘011
’. Bit T6M.0 (T6CON.3) selects the active level of the gate input.
B
B
In gated timer mode the same options for the input frequency as for the timer mode are
available. However, the input clock to the timer in this mode is gated by the external input
line T6IN (Timer T6 External Input).
x = 6
Figure 14-17 Block Diagram of Core Timer T6 in Gated Timer Mode
If T6M.0 = ‘0’ the timer is enabled when T6IN shows a low level. A high level at this line
stops the timer. If T6M.0 = ‘1’ line T6IN must have a high level in order to enable the
timer. In addition, the timer can be turned on or off by software using bit T6R. The timer
will only run, if T6R = ‘1’ and the gate is active. It will stop, if either T6R = ‘0’ or the gate
is inactive.
Note: A transition of the gate signal at line T6IN does not cause an interrupt request.
Timer 6 in Counter Mode
Counter mode for the core timer T6 is selected by setting bit field T6M in register T6CON
to ‘001
’. In counter mode timer T6 is clocked by a transition at the external input line
B
T6IN. The event causing an increment or decrement of the timer can be a positive, a
negative, or both a positive and a negative transition at this line. Bit field T6I in control
register T6CON selects the triggering transition (see table below).
Data Sheet
208
2003-03-31

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