PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 563

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

22.11.6
The device control register includes control and status bits which indicate the current
status of the USB module and the status of the USB bus.
Reset value: 00000000
RSM
DINIT
SUSP
SWR
UCLK
Note: A software reset initiated by setting bit SWR to ’1’, which should be done 4 clock
Data Sheet
09
H
Bit
cycles after UCLK has been set to ’1’, clears bit UCLK. This means UCLK has to
be set to ’1’ again. Note that this reinforcement of DCR.UCLK has to be
programmed 20 clock cycles after SWR has been set.
7
0
r
Device Control Register (DCR)
Resume Bus Activity
When the USB device is in suspend mode, setting bit RSM resumes bus
activity. In response to this action, the USB will deassert the suspend bit
and perform the remote wake-up operation. Writing 0 to RSM has no
effect, the bit is reset if bit SUSP is 0.
Device Initialization in Progress
At the end of a software reset, bit DINIT is set by hardware. After software
reset of the USB module, it must be initialized by the CPU. When DINIT
is set after a software reset, 6 bytes for each endpoint must be written to
SFR USBVAL0. After the 96th byte, bit DONE0 has to be set by software.
Bit DINIT is reset by software after a successful initialization sequence.
Suspend Mode
This bit is set when the USB is idle for more than 3 ms. It will remain set
until there is a non idle state on the USB cable or when bit RSM is set.
In addition to SUSP an interrupt can be generated when the suspend
mode begins (DIRR.SBI) and when it ends (DIRR.SEI)
Software Reset
Setting bit SWR initiates a software reset operation of the USB device.
This bit is cleared by hardware after a successful reset operation. SWR
can not be reset by software.
USB Clock Enable
Setting bit UCLK to "0" disables the 48 MHz USB clock signal (see Figure
4-1)
6
0
r
B
SWR
rw
5
SUSP
4
r
563
Function
DINIT
3
r
RSM
rw
2
UCLK
Address: 09
rw
1
USB Module
PSB 21473
2003-03-31
INCA-D
H
0
0
r