PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 242

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
15.1.5.3 Asynchronous Reception
Asynchronous reception is initiated by a falling edge (1-to-0 transition) on pin RXD, pro-
vided that bits S0CON_R and S0CON_REN are set. The receive data input pin RXD is
sampled at 16 times the rate of the selected baudrate. A majority decision of the 7th, 8th
and 9th sample determines the effective bit value. This avoids erroneous results that
may be caused by noise.
If the detected value is not a '0' when the start bit is sampled, the receive circuit is reset
and waits for the next 1-to-0 transition at pin RXD. If the start bit proves valid, the receive
circuit continues sampling and shifts the incoming data frame into the receive shift reg-
ister.
When the last stop bit has been received, the content of the receive shift register is trans-
ferred to the receive data buffer register S0RBUF. Simultaneously, the receive interrupt
request line RIR is activated after the 9th sample in the last stop bit time slot (as pro-
grammed), regardless whether valid stop bits have been received or not. The receive cir-
cuit then waits for the next start bit (1-to-0 transition) at the receive data input pin.
The receiver input pin RXD must be configured for input.
Asynchronous reception is stopped by clearing bit S0CON_REN. A currently received
frame is completed including the generation of the receive interrupt request and an error
interrupt request, if appropriate. Start bits that follow this frame will not be recognized.
Note: In wake-up mode received frames are only transferred to the receive buffer
15.1.5.4 IrDA Mode
The duration of the IrDA pulse is normally 3/16 of a bit period. The IrDA standard also
allows the pulse duration being independent of the baudrate or bit period. In this case
the transmitted pulse has always the width corresponding to the 3/16 pulse width at
115.2 kBaud which is 1.627 µs. Both, bit period dependend or fixed IrDA pulse width gen-
eration can be selected. The IrDA pulse width mode is selected by bit PMW_IRPW.
In case of fixed IrDA pulse width generation, the lower 8 bits in register PMW are used
to adapt the IrDA pulse width to a fixed value of e.g. 1.627 µs. The fixed IrDA pulse width
is generated by a programmable timer as shown in Figure 15-7.
register, if the 9th bit (the wake-up bit) is ‘1’. If this bit is ‘0’, no receive interrupt
request will be activated and no data will be transferred.
The Asynchronous / Synchr. Serial Interface
242
PSB 21473
2003-03-31
INCA-D