PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 296

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
Every received frame is stored in RFIFO (first byte after opening flag to CRC field).
Additional information can be read from RSTA.
Transparent Mode 1 (MDS2-0 = ’111’).
Characteristics:
A comparison is performed on the first byte after the opening flag with SAP1, SAP2 and
“group” SAPI (FE
Additional information can be read from RSTA.
Transparent Mode 2 (MDS2-0 = ’101’).
Characteristics:
A comparison is performed only on the second byte after the opening flag, with TEI1,
TEI2 and group TEI (FF
Additional information can be read from RSTA.
Extended Transparent Mode (MDS2-0 = ’100’ and SRA = ’0’).
Characteristics:
In extended transparent mode fully transparent data transmission/reception without
HDLC framing is performed i.e. without FLAG generation/recognition, CRC generation/
check, bitstuffing mechanism. This allows user specific protocol variations.
The transmitter sends the data out of the FIFO without manipulation. Transmission is
always IOM-frame aligned and byte aligned, i.e. transmission starts in the first selected
channel (e.g. B1, B2, D) of the next IOM-frame.
The FIFO indications and commands are the same as in other modes.
If the microcontroller sets XTF & XME the transmitter responds with an XPR interrupt
after sending the last byte, then it returns to its idle state (sending continuous ‘1’).
If the cts (clear to send) signal is set to “0” during transmission the transparent HDLC
controller responds always with an XMR (transmit message repeat) interrupt and stops
transmission.
If the microcontroller fails to respond to an XPR interrupt in time and the transmitter runs
out of data then it will assert an XDU (transmit data underrun) interrupt.
The reception is IOM-frame aligned and byte aligned, like transmission, i.e. reception
starts in the first selected channel (B1, B2, D on IOM-2) of the next IOM frame. The FIFO
indications and commands are the same as in other modes.
All incoming data bytes are stored in the RFIFO. If the FIFO is full an RFO interrupt is
asserted (EXMR.SRA = ’0’).
Note: In the extended transparent mode the EXMR register has to be set to ’xxx00000’
H
/FC
SAPI recognition
TEI recognition
fully transparent
H
). In the case of a match, all following bytes are stored in RFIFO.
H
). In case of a match the rest of the frame is stored in the RFIFO.
IOM-2 Handler, TIC/CI Handler and HDLC Controller
296
PSB 21473
2003-03-31
INCA-D