LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 102

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

7.10 SERIAL IRQ
The LPC47M192 supports the serial interrupt to transmit interrupt information to the host system. The serial interrupt
scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0.
Timing Diagrams For SER_IRQ Cycle
A) Start Frame timing with source sampled a low pulse on IRQ1
Note:
Note 1: Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge
B) Stop Frame Timing with Host using 17 SER_IRQ sampling period
Note:
Note 1: The next SER_IRQ cycle’s Start Frame pulse may or may not start immediately after the turn-around clock
Note 2: There may be none, one or more Idle states during the Stop Frame.
Note 3: Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
SER_IRQ Cycle Control
There are two modes of operation for the SER_IRQ Start Frame
1) Quiet (Active) Mode: Any device may initiate a Start Frame by driving the SER_IRQ low for one clock, while the
SER_IRQ is Idle. After driving low for one clock the SER_IRQ must immediately be tri-stated without at any time
driving high. A Start Frame may not be initiated while the SER_IRQ is Active. The SER_IRQ is Idle between Stop
and Start Frames. The SER_IRQ is Active between Start and Stop Frames. This mode of operation allows the
SER_IRQ to be Idle when there are no IRQ/Data transitions which should be most of the time.
Once a Start Frame has been initiated the Host Controller will take over driving the SER_IRQ low in the next clock
and will continue driving the SER_IRQ low for a programmable period of three to seven clocks. This makes a total
low pulse width of four to eight clocks. Finally, the Host Controller will drive the SER_IRQ back high for one clock,
then tri-state.
Any SER_IRQ Device (i.e., The LPC47M192) which detects any transition on an IRQ/Data line for which it is
responsible must initiate a Start Frame in order to update the Host Controller unless the SER_IRQ is already in an
SER_IRQ Cycle and the IRQ/Data transition can be delivered in that SER_IRQ Cycle
SMSC DS – LPC47M192
PCI_CLK
SER_IRQ
PCI_CLK
SER_IRQ
Drive Source
H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample
hierarchy in a synchronous bridge design.
H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle
of the Stop Frame.
Driver
S
FRAME
None
IRQ14
R
IRQ1
SL
or
H
T
START
S
Host Controller
START FRAME
IRQ15
H
IRQ15
FRAME
R
1
DATASHEET
T
R
S
IOCHCK#
None
FRAME
Page 102
T
R
IRQ0 FRAME IRQ1 FRAME
T
S
None
I
R
2
STOP FRAME
Host Controller
T
STOP
H
S
IRQ1
1
R
R
T
T
NEXT CYCLE
IRQ2 FRAME
S
None
START
R
Rev. 03/30/05
T
3