LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 223

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

16 APPENDIX C - TEST MODE
The LPC47M192 provides board test capability through the implementation of two XNOR chains. One chain is
dedicated to the Super I/O portion of the chip (pins 1 – 100) and the second chain is dedicated solely to the Hardware
Monitoring Block (pins 101 – 128).
XNOR-Chain Test Mode
XNOR-Chain test structure allows users to confirm that all pins are in contact with the motherboard during assembly
and test operations. See FIGURE 46 below. When the chip is in the XNOR chain test mode, setting the state of any
of the input pins to the opposite of its current state will cause the output of the chain to toggle.
The XNOR-Chain test structure must be activated to perform these tests. When the XNOR-Chain is activated, the
LPC47M192 pin functions are disconnected from the device pins, which all become input pins except for one output
pin at the end of XNOR-Chain.
The tests that are performed when the XNOR-Chain test structure is activated require the board-level test hardware
to control the device pins and observe the results at the XNOR-Chain output pin.
16.1 Super I/O Block
16.1.1 BOARD TEST MODE
Board test mode can be entered as follows:
On the rising (deasserting) edge of PCI_RESET#, drive LFRAME# low and drive LAD[0] low.
Exit board test mode as follows:
On the rising (deasserting) edge of PCI_RESET#, drive either LFRAME# or LAD[0] high.
See the “XNOR-Chain Test Mode” section above for a description of this board test mode.
The PCI_RESET# pin is not included in the XNOR-Chain. The XNOR-Chain output pin# is 85, TXD1. See the
following subsections for more details.
Pin List of Super I/O XNOR Chain
Pins 1 to 100 on the chip are inputs to the first XNOR chain, with the exception of the following:
SMSC DS – LPC47M192
I/O#1
1.
2.
3.
4.
VCC (pins 53, 65, & 93), VTR (pin 18), and VREF (pin 44).
VSS (pins 7, 31, 60, & 76) and AVSS (pin 40).
TXD1 (pin 85) This is the chain output.
nPCI_RESET (pin 26).
I/O#2
FIGURE 46 - XNOR-CHAIN TEST STRUCTURE
DATASHEET
I/O#3
Page 223
I/O#n
XNor
Out
Rev. 03/30/05