LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 4

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

1
2
3
4
5
6
7
SMSC DS – LPC47M192
4.1
4.2
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7.1
7.2
7.3
7.4
GENERAL DESCRIPTION .................................................................................................................... 3
PIN LAYOUT ........................................................................................................................................ 10
PIN CONFIGURATION ........................................................................................................................ 11
DESCRIPTION OF PIN FUNCTIONS.................................................................................................. 12
4.2.1
4.2.2
BLOCK DIAGRAM............................................................................................................................... 22
POWER FUNCTIONALITY .................................................................................................................. 23
6.1.1
6.3.1
6.4.1
6.6.1
6.6.2
FUNCTIONAL DESCRIPTION............................................................................................................. 27
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.3.8.1
7.3.8.2
7.3.9.1
7.3.9.2
7.3.9.3
7.3.9.4
7.3.9.5
7.3.9.6
7.3.10.1
B
P
VCC/HVCC P
VREF P
VTR S
32.768
I
M
P
S
H
LPC I
F
NTERNAL
LOPPY
UFFER
INS
OWER
UPER
OST
AXIMUM
Super I/O Pins ........................................................................................................................................20
Hardware Monitoring Block Pins.............................................................................................................21
3 VOLT OPERATION / 5 VOLT TOLERANCE .......................................................................................23
Trickle Power Functionality .....................................................................................................................23
Indication of 32KHZ Clock ......................................................................................................................25
Super I/O Functions................................................................................................................................25
Hardware Monitoring Block Functions ....................................................................................................26
LPC Interface Signal Definition...............................................................................................................28
LPC Cycles.............................................................................................................................................28
Field Definitions ......................................................................................................................................28
LFRAME# Usage....................................................................................................................................28
I/O Read and Write Cycles .....................................................................................................................29
DMA Read and Write Cycles ..................................................................................................................29
DMA Protocol .........................................................................................................................................29
POWER MANAGEMENT .......................................................................................................................29
SYNC Protocol .......................................................................................................................................29
FDC Internal Registers ...........................................................................................................................31
STATUS REGISTER ENCODING ..........................................................................................................41
Instruction Set.........................................................................................................................................48
DATA TRANSFER COMMANDS............................................................................................................54
DIRECT SUPPORT FOR TWO FLOPPY DRIVES.................................................................................64
T
NTERFACE
P
LPC TRANSFERS ..............................................................................................................................30
HAT
UPPORT
I/O R
ROCESSOR
K
M
D
N
IN
CLOCKRUN Protocol .................................................................................................................................... 29
LPCPD Protocol.............................................................................................................................................. 29
Typical Usage ................................................................................................................................................. 29
SYNC Timeout ............................................................................................................................................... 30
SYNC Patterns and Maximum Number of SYNCS ........................................................................................ 30
SYNC Error Indication.................................................................................................................................... 30
I/O and DMA START Fields .......................................................................................................................... 30
Reset Policy..................................................................................................................................................... 30
Wait State Requirements................................................................................................................................. 30
H
ANAGEMENT
ISK
AME
PWRGOOD..................................................................................................................... 25
C
........................................................................................................................................ 23
Z
R
URRENT
T
EQUIRE
EGISTERS
C
RICKLE
OWER
D
................................................................................................................................. 23
ONTROLLER
...............................................................................................................................28
ESCRIPTIONS
I
NTERFACE
V
E
........................................................................................................................ 23
C
ALUES
XTERNAL
E
..................................................................................................................... 27
LOCK
VENTS
.............................................................................................................. 31
............................................................................................................. 25
I
........................................................................................................... 20
NPUT
(LPC) ............................................................................................... 27
(PME/SCI)....................................................................................... 26
P
TABLE OF CONTENTS
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DATASHEET
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R
ESISTORS
Page 4
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Rev. 03/30/05