LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 43

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

RESET
There are three sources of system reset on the FDC: the PCI_RESET# pin, a reset generated via a bit in the DOR,
and a reset generated via a bit in the DSR. At power on, a Power On Reset initializes the FDC. All resets take the
FDC out of the power down state.
All operations are terminated upon a PCI_RESET#, and the FDC enters an idle state. A reset while a disk write is in
progress will corrupt the data and CRC.
On exiting the reset state, various internal registers are cleared, including the Configure command information, and
the FDC waits for a new command. Drive polling will start unless disabled by a new Configure command.
PCI_RESET# Pin (Hardware Reset)
The PCI_RESET# pin is a global reset and clears all registers except those programmed by the Specify command.
The DOR reset bit is enabled and must be cleared by the host to exit the reset state.
DOR Reset vs. DSR Reset (Software Reset)
These two resets are functionally the same. Both will reset the FDC core, which affects drive status information and
the FIFO circuits. The DSR reset clears itself automatically while the DOR reset requires the host to manually clear it.
DOR reset has precedence over the DSR reset. The DOR reset is set automatically upon a pin reset. The user must
manually clear this reset bit in the DOR to exit the reset state.
MODES OF OPERATION
The FDC has three modes of operation, PC/AT mode, PS/2 mode and Model 30 mode. These are determined by the
state of the Interface Mode bits in LD0-CRF0[3,2].
PC/AT mode
The PC/AT register set is enabled, the DMA enable bit of the DOR becomes valid (controls the interrupt and DMA
functions), and DENSEL is an active high signal.
PS/2 mode
This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the DOR becomes a
“don’t care”. The DMA and interrupt functions are always enabled, and DENSEL is active low.
Model 30 mode
This mode supports PS/2 Model 30 configuration and register set. The DMA enable bit of the DOR becomes valid
(controls the interrupt and DMA functions), and DENSEL is active low.
SMSC DS – LPC47M192
Page 43
Rev. 03/30/05
DATASHEET