LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 65

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

Note:
information.
REGISTER DESCRIPTION
Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial ports are
defined by the configuration registers (see “Configuration” section).
sequentially increasing addresses above these base addresses. The LPC47M192 contains two serial ports, each of
which contain a register set as described below.
*Note: DLAB is Bit 7 of the Line Control Register
The following section describes the operation of the registers.
RECEIVE BUFFER REGISTER (RB)
Address Offset = 0H, DLAB = 0, READ ONLY
This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted and received
first. Received data is double buffered; this uses an additional shift register to receive the serial data stream and
convert it to a parallel 8 bit word which is transferred to the Receive Buffer register. The shift register is not
accessible.
TRANSMIT BUFFER REGISTER (TB)
Address Offset = 0H, DLAB = 0, WRITE ONLY
This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an additional
shift register (not accessible) to convert the 8 bit data word to a serial format. This shift register is loaded from the
Transmit Buffer when the transmission of the previous byte is complete.
INTERRUPT ENABLE REGISTER (IER)
Address Offset = 1H, DLAB = 0, READ/WRITE
The lower four bits of this register control the enables of the five interrupt sources of the Serial Port interrupt. It is
possible to totally disable the interrupt system by resetting bits 0 through 3 of this register. Similarly, setting the
appropriate bits of this register to a high, selected interrupts can be enabled. Disabling the interrupt system inhibits
the Interrupt Identification Register and disables any Serial Port interrupt out of the LPC47M192. All other system
functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of
the Interrupt Enable Register are described below.
Bit 0
This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic
“1”.
SMSC DS – LPC47M192
The UARTs 1 and 2 may be configured to share an interrupt. Refer to the Configuration section for more
DLAB*
X
X
X
X
X
X
X
0
0
0
1
1
A2
0
0
0
0
0
0
0
0
1
1
1
1
Table 28 – Addressing the Serial Port
A1
0
0
0
1
1
1
0
0
1
1
0
0
DATASHEET
A0
0
0
1
0
0
1
0
1
0
1
0
1
Page 65
Receive Buffer (read)
Transmit Buffer (write)
Interrupt Enable (read/write)
Interrupt Identification (read)
FIFO Control (write)
Line Control (read/write)
Modem Control (read/write)
Line Status (read/write)
Modem Status (read/write)
Scratchpad (read/write)
Divisor LSB (read/write)
Divisor MSB (read/write
REGISTER NAME
The Serial Port registers are located at
Rev. 03/30/05