LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 113

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

PIN#
41
42
43
45
46
47
50
51
52
54
55
61
62
63
64
17
32
33
34
35
36
37
38
39
1
2
events are enabled. Note that the keyboard and mouse isolation bits only prevent the internal 8042 in the part from
setting these status bits.
Case 1: Keyboard and/or Mouse Powered by VTR
The KBD and/or MOUSE status bits will be set upon a VTR POR if the keyboard and/or mouse are powered by VTR.
In this case, an IO_PME# will not be generated, since the keyboard and mouse PME enable bits are reset to zero on
a VTR POR. The BIOS software needs to clear these PME status bits after power-up.
Case 2: Keyboard and/or Mouse Powered by VCC
The KBD and/or MOUSE status bits will be set upon a VCC POR if the keyboard and/or mouse are powered by VCC.
In this case, an IO_PME# will be generated if the enable bits were set for wakeup, since the keyboard and mouse
PME enable bits are VTR powered. Therefore, if the keyboard and mouse are powered by VCC, the enable bits for
keyboard and mouse events should be cleared prior to entering a sleep state where VCC is removed (i.e., S3) to
prevent a false PME from being generated. In this case, the keyboard and mouse should only be used as PME
and/or wake events from the S0 and/or S1 states. The BIOS software needs to clear these PME status bits after
power-up.
7.12 GENERAL PURPOSE I/O
The LPC47M192 provides a set of flexible Input/Output control functions to the system designer through the 37
independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform basic I/O and many of
them can be individually enabled to generate an SMI and a PME.
7.12.1 GPIO PINS
The following pins include GPIO functionality. These pins are defined in the table below. All GPIOs default to the
GPIO function except for GP34 and GP35 which default to IRRX2 and IRTX2.
SMSC DS – LPC47M192
GP10/J1B1
GP11/J1B2
GP12 /J2B1
GP13 /J2B2
GP14 /J1X
GP15 /J1Y
GP16 /J2X
GP17 /J2Y
GP20/P17
GP21/P16/nDS1
GP22/P12/nMTR1
GP24/SYSOPT
GP25/MIDI_IN
GP26/MIDI_OUT
GP27/nIO_SMI
GP30/FAN_TACH2
GP31/FAN_TACH1
GP32/FAN2
GP33/FAN1
IRRX2/GP34
IRTX2/GP35
GP36/nKBDRST
GP37/A20M
GP40/DRVDEN0
GP41/DRVDEN1
GP42/nIO_PME
Alternate Funcs)
(Default Func/
PIN NAME
GPIO PIN
WELL
PWR
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VTR
VTR
Out – low
Out – low
Out – low
RESET
PCI
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCC
POR
Out–
Out–
Out–
low
low
low
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DATASHEET
POR
Out -
VTR
low
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
OFFS
(hex)
Page 113
REG
ET
2A
2B
2C
2D
3A
3B
3C
3D
23
24
25
26
27
28
29
2F
30
31
32
33
34
35
36
37
38
39
GP10
GP11
GP12
GP13
GP14
GP15
GP16
GP17
GP20
GP21
GP22
GP24
GP25
GP26
GP27
GP30
GP31
GP32
GP33
GP34
GP35
GP36
GP37
GP40
GP41
GP42
REG
RESET
GPIO REGISTER
0x00
0x00
0x04
PCI
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
POR
0x00
0x00
0x04
VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
POR
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x05
0x04
0x01
0x01
0x01
0x01
0x01
VTR
RESET
SOFT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nIO_SMI/PME
SMI/nIO_PME
SMI/PME
SMI/PME
SMI/PME
SMI/PME
SMI/PME
SMI/PME
SMI/PME
SMI/PME
SMI/PME
SMI/PME
SMI/PME
SMI/PME
PME
PME
PME
PME
PME
PME
PME
PME
SMI
Rev. 03/30/05
-
-
-
-
NOTES
1, 2
1, 2
3, 4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1