LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 144

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

SMSC DS – LPC47M192
PME_STS4
Default = 0x00
(Note 6)
PME_STS5
Default = 0x00
(Note 6)
N/A
on VTR POR
on VTR POR
NAME
REG OFFSET
(R/W)
(R/W)
(hex)
(R)
07
08
09
DATASHEET
PME Wake Status Register 4
This register indicates the state of the individual PME
wake sources, independent of the individual source
enables or the PME_En bit.
If the wake source has asserted a wake event, the
associated PME Wake Status bit will be a “1”.
Bit[0] GP30
Bit[1] GP31
Bit[2] GP32
Bit[3] GP33
Bit[4] GP41
Bit[5] GP43
Bit[6] GP60
Bit[7] GP61
The PME Wake Status register is not affected by Vcc
POR, SOFT RESET or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any
bit in PME Wake Status Register has no effect.
PME Wake Status Register 5
This register indicates the state of the individual PME
wake sources, independent of the individual source
enables or the PME_En bit.
If the wake source has asserted a wake event, the
associated PME Wake Status bit will be a “1”.
Bit[0] GP50
Bit[1] GP51
Bit[2] GP52
Bit[3] GP53
Bit[4] GP54
Bit[5] GP55
Bit[6] GP56
Bit[7] GP57
The PME Wake Status register is not affected by Vcc
POR, SOFT RESET or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any
bit in PME Wake Status Register has no effect.
Bits[7:0] Reserved – reads return 0
Page 144
DESCRIPTION
Rev. 03/30/05