LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 34

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

BIT 7 nDRV2
Active low status of the DRV2 disk interface input. Note: This function is not supported.
DIGITAL OUTPUT REGISTER (DOR)
Address 3F2 READ/WRITE
The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the
DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be
written to at any time.
BIT 0 and 1 DRIVE SELECT
These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time.
BIT 2 nRESET
A logic “0” written to this bit resets the Floppy disk controller. This reset will remain active until a logic “1” is written to
this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR
register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this
register is a valid method of issuing a software reset.
BIT 3 DMAEN
PC/AT and Model 30 Mode:
Writing this bit to logic “1” will enable the DMA and interrupt functions. This bit being a logic “0” will disable the DMA
and interrupt functions. This bit is a logic “0” after a reset and in these modes.
PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset, this bit will be cleared
to a logic “0”.
BIT 4 MOTOR ENABLE 0
This bit controls the MTR0 disk interface output. A logic “1” in this bit will cause the output pin to go active.
BIT 5 MOTOR ENABLE 1
This bit controls the MTR1 disk interface output. A logic “1” in this bit will cause the output pin to go active.
SMSC DS – LPC47M192
RESET
COND.
Bit 5
X
1
0
MOT
EN3
DIGITAL OUTPUT
7
0
Bit 4
REGISTER
X
1
0
Bit1
MOT
EN2
X
0
0
6
0
DRIVE
0
1
Table 3 – Internal 2 Drive Decode – Normal
Bit 0
0
1
X
MOT
EN1
DRIVE SELECT OUTPUTS
DATASHEET
5
0
nDS1
1
0
1
(ACTIVE LOW)
Page 34
MOT
EN0
4
0
DOR VALUE
1CH
2DH
nDS0
0
1
1
DMAEN
3
0
MOTOR ON OUTPUTS
nMTR1
nBIT 5
nBIT 5
nBIT 5
nRESET
(ACTIVE LOW)
2
0
nMTR0
DRIVE
nBIT 4
nBIT 4
nBIT 4
SEL1
1
0
DRIVE
SEL0
Rev. 03/30/05
0
0