LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 109

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

7.11.8 DEFAULT RESET CONDITIONS
The LPC47M192 has one source of hardware reset: an external reset via the PCI_RESET# pin. Refer to Table 52 for
the effect of each type of reset on the internal registers.
GATEA20 AND KEYBOARD RESET
The LPC47M192 provides two options for GateA20 and Keyboard Reset: 8042 Software Generated GateA20 and
KRESET and Port 92 Fast GateA20 and KRESET.
PORT 92 FAST GATEA20 AND KEYBOARD RESET
Port 92 Register
This port can only be read or written if Port 92 has been enabled via bit 2 of the KRST_GA20 Register (Logical
Device 7, 0xF0) set to 1.
This register is used to support the alternate reset (nALT_RST) and alternate A20 (ALT_A20) functions.
SMSC DS – LPC47M192
BIT
7:6
5
4
3
2
1
0
driven low. Writing a 1 to this bit causes the ALT_A20 signal to be driven high.
function. This function provides an alternate means to reset the system CPU to
effect a mode switch from Protected Virtual Address Mode to the Real Address
Mode. This provides a faster means of reset than is provided by the Keyboard
controller. This bit is set to a 0 by a system reset. Writing a 1 to this bit will cause
the nALT_RST signal to pulse active (low) for a minimum of 1 µs after a delay of
500 ns. Before another nALT_RST pulse can be generated, this bit must be written
back to a 0.
ALT_A20 Signal control. Writing a 0 to this bit causes the ALT_A20 signal to be
Alternate System Reset. This read/write bit provides an alternate system reset
Host I/F Status Reg
Host I/F Data Reg
DESCRIPTION
MCLK
MDAT
KDAT
KCLK
Name
Location
Default Value
Attribute
Size
DATASHEET
Reserved. Returns a 1 when read
Reserved. Returns a 0 when read
Reserved. Returns a 0 when read
Reserved. Returns a 1 when read
Reserved. Returns 00 when read
PORT 92 REGISTER
N/A: Not Applicable
Table 52 - Resets
Page 109
FUNCTION
Port 92
92h
24h
Read/Write
8 bits
HARDWARE RESET
(PCI_RESET#)
Low
Low
Low
Low
00H
N/A
Rev. 03/30/05