LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 40

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

BITS 1 – 2 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual
data rates. The data rate select bits are
hardware reset.
BITS 3 – 6 UNDEFINED
Always read as a logic “1”
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value
programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).
Model 30 Mode
BITS 0 – 1 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual
data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware
reset.
BIT 2 NOPREC
This bit reflects the value of NOPREC bit set in the CCR register.
BIT 3 DMAEN
This bit reflects the value of DMAEN bit set in the DOR register bit 3.
BITS 4 – 6 UNDEFINED
Always read as a logic “0”
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value
programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).
CONFIGURATION CONTROL REGISTER (CCR)
Address 3F7 WRITE ONLY
PC/AT and PS/2 Modes
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy controller. See Table 8 for the appropriate values.
BIT 2 – 7 RESERVED
SMSC DS – LPC47M192
Should be set to a logical “0”
RESET
RESET
COND.
COND.
DSK CHG
N/A
N/A
7
7
0
N/A
6
0
0
6
0
DATASHEET
N/A
unaffected by
5
0
0
5
0
Page 40
N/A
4
0
0
4
0
a software reset, and are set to 250 Kbps after a
DMAEN NOPREC DRATE
N/A
3
0
3
0
N/A
2
0
2
0
DRATE
SEL1
SEL1
1
1
1
1
DRATE
DRATE
SEL0
SEL0
0
0
0
0
Rev. 03/30/05