LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 122

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

Fan Speed Control Summary
The following table illustrates the different modes for the fans.
Note 1: This is FANx Register Bit 0
Note 2: This is Fan Control Register Bit 2 or 3
Note 3: This is Fan Control Register Bit 0 or 1
Note 4: This is FANx Register Bit 7
FANx Registers
The FAN1 and FAN2 Registers are located at 0x56 and 0x57 from base I/O in Logical Device A. The bits are defined
below. See the register description in the “Runtime Registers” section.
Fan Control Register
The Fan Control Register is located at 0x58 from base I/O in Logical Device A. The bits are defined below. See the
register description in the “Runtime Registers” section.
7.15.2 FAN SPEED MONITORING
The LPC47M192 monitors the speed of the fans by utilizing fan tachometer input signals from fans equipped with
tachometer outputs. There are two pins that can be configured as the fan tachometer inputs (pins 51 and 52) which
SMSC DS – LPC47M192
Fan x Clock Select Bit, D7
The Fan x Clock select bit in the FANx registers is used with the Fan x Clock Source Select and the Fan x
Clock Multiplier bits in the Fan Control register to determine the fan speed F
Duty Cycle Control for Fan x, Bits D6 – D1
The Duty Cycle Control (DCC) bits determine the fan duty cycle. The LPC47M192 has ≈ 1.56% duty cycle
resolution. When DCC = “000000” (min. value), F
F
duty cycle (%) is (DCC/64) x 100.
Fan x Clock Control, Bit D0
The Fan x Clock Control bit D0 is used to override the Duty Cycle Control for Fan x bits and force F
always high. When D0 = “0”, the DCC bits determine the F
high, regardless of the state of the DCC bits.
Fan x Count Divisor, Bits D7-D6 / D5-D4
Fan x Count Divisor bit in Fan Control Register is used to determine fan tachometer count. The choices for
the divisor are 1, 2, 4 and 8. See “Fan Tachometer Input” section.
Fan x Clock Multiplier, Bits D3 / D2
The Fan x Clock Multiplier bit is used with the Fan x Clock Source Select bit in the Fan Control Register and
the Fan x Clock Select bit in Fan register to determine the F
no clock multiplier is used. When the Fan x Clock Multiplier bit = “1”, the clock speed determined by the Fan
x Clock Source Select bit is doubled.
Fan x Clock Source Select, Bits D1 / D0
The Fan x Clock Source Select and the Fan x Clock Multiplier bits in the Fan Control register is used with
the Fan x Clock Select bit in the Fan x registers to determine the fan speed F
(Note 1)
Control
OUT
Clock
FANx
Bit
0
0
0
0
0
0
0
0
0
1
is almost always high; i.e., high for 63/64
Multiplier
(Note 2)
Clock
FANx
Bit
X
X
0
0
0
0
1
1
1
1
Select Bit
(Note 3)
Source
FANx
Clock
Table 56 - Different Modes for Fan
X
X
0
0
1
1
0
0
1
1
DATASHEET
Select Bit
(Note 4)
Clock
FANx
X
X
0
1
0
1
0
1
0
1
Page 122
th
and low for 1/64
OUT
0Hz – HIGH
0Hz – LOW
is always low. When DCC is “111111” (max. value),
15.625kHz
23.438kHz
46.876kHz
31.25kHz
120Hz
40Hz
60Hz
80Hz
F
out
OUT
OUT
. When the Fan x Clock Multiplier bit = “0”,
duty cycle. When D0 = 1, F
th
of the F
6-Bit Duty
bits[6:1]
Control
(DCC)
Cycle
1-63
0
-
OUT
OUT
OUT
. See Table 56 above.
. See Table 56 above.
period. Generally, the F
Duty Cycle
(DCC/64)
x 100
(%)
-
-
OUT
Rev. 03/30/05
is always
OUT
OUT