LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 131

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

FIELD:
Bits:
Send Byte
The Send Byte protocol is used to set the Internal Address Register to the correct register in the Hardware Monitor
Block. No data is transferred for a Send Byte protocol. The Send Byte can be followed by the Receive Byte protocol
described below in order to read data from the register. The send byte protocol cannot be used to write data - if data
is to be written to a register then the write byte protocol must be used as described in subsection above. The send
byte protocol is shown in the table below.
Receive Byte
The Receive Byte protocol is used to read data from the registers when the register address is known to be at the
desired address (using the Internal Address Register). This is used when the register address has been written to
the desired address using the Send Byte protocol. This can be used for successive reads of the same register. The
data will only be read if the protocol shown in Table 4 is performed correctly. Only one byte is transferred at time for
a Receive Byte protocol.
7.18.2.1.2
The slave address is the unique address for the Hardware Monitor Block that identifies the device on SMBus.
The Hardware Monitor Block’s slave address is determined by the level on the A0 pin. The level on this pin forms the
LSB of the 7-bit address 0101_10x. This pin may be used to support up to 2 Hardware Monitor Blocks in a given
system.
The upper 6 bits of the Hardware Monitor Block’s slave address are hardwired in the Hardware Monitor Block.
7.18.2.1.3
Registers that are accessed with an invalid protocol will not be updated. A register will only be updated following a
valid protocol. The only valid protocols are the read byte, receive byte and write byte protocols described above.
The only valid slave address is determined by the level on the A0 pin as the LSB of the address 0101_10x.
The only valid registers for a read or write protocol are the registers shown in the Registers Section. Reserved
registers are not considered valid registers.
Attempting to communicate with the Hardware Monitor Block over SMBus with an invalid slave address, invalid
register address or invalid protocol will result in no response, and the SMBus Slave Interface will return to the idle
state.
7.18.2.1.4
The Hardware Monitor Block will not respond to a general call address of 0000_000.
SMSC DS – LPC47M192
START
1
Slave Address
Invalid Protocol Response Behavior
General Call Address Response
SLAVE
ADDR
7
FIELD:
FIELD: START
Bits:
Bits:
WR
1
START
1
1
Table 60 - SMBus Receive Byte Protocol
ACK
Table 58 - SMBus Read Byte Protocol
Table 59 - SMBus Send Byte Protocol
1
SLAVE
SLAVE
ADDR
ADDR
DATASHEET
ADDR
REG.
7
7
8
ACK START
WR
RD
Page 131
1
1
1
ACK
ACK
1
1
1
DATA
REG.
ADDR
REG.
8
SLAVE
8
ADDR
7
NACK
ACK
1
1
RD ACK
1
STOP
STOP
1
1
1
DATA
REG.
8
NACK
1
Rev. 03/30/05
STOP
1