LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 27

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

7
7.1 Super I/O Registers
7.2 Host Processor Interface (LPC)
Note:
Note 1: Logical Device A is refered to as the Runtime Register block or PME Block and may be used
interchangeably throughout this document.
SMSC DS – LPC47M192
The following sections describe the functional blocks located in the LPC47M192 (see FIGURE 1). All the
functional blocks are dedicated to the Super I/O portion of the chip, except for the Hardware Monitoring block.
The Hardware Monitoring block is maintained separately from the Super I/O components and is defined in
section 7.18 − Hardware Monitoring Interface. It is powered by HVCC and all its registers are accessed through
an Internal Address register located in the Hardware Monitoring block (see section 10 − Registers for Hardware
Monitoring Block). The various Super I/O components are described in the following sections and their registers
are implemented as typical Plug-and-Play components (see section 9 − CONFIGURATION).
It should be noted that there are two main interfaces used to access the components of this chip. The LPC
interface is used to access the Super I/O registers and the SMBus is used to access the Hardware Monitoring
registers.
FUNCTIONAL DESCRIPTION
The address map, shown below in Table 1 shows the addresses of the different blocks of the Super I/O
immediately after power up. The base addresses of the FDC, serial and parallel ports, PME register block,
Game port and configuration register block can be moved via the configuration registers. Some addresses are
used to access more than one register.
The host processor communicates with the LPC47M192 through a series of read/write registers via the LPC
interface. The port addresses for these registers are shown in Table 1. Register access is accomplished
through I/O cycles or DMA transfers. All registers are 8 bits wide.
Refer to the configuration register descriptions for setting the base address.
Base+(0-5) and +(7)
Base+(0-7)
Base1+(0-7)
Base2+(0-7)
Base+(0-3)
Base+(0-7)
Base+(0-3), +(400-402)
Base+(0-7), +(400-402)
60, 64
Base + 0
Base + (0-5F)
Base + (0-1)
Base + (0-1)
ADDRESS
Table 1 – Super I/O Block Addresses
DATASHEET
Floppy Disk
Serial Port Com 1
Serial Port Com 2
Parallel Port
SPP
EPP
ECP
ECP+EPP+SPP
KYBD
Game Port
Runtime Registers
MPU-401
Configuration
BLOCK NAME
Page 27
0
4
5
3
7
9
A
B
LOGICAL
DEVICE
Note 1
NOTES
Rev. 03/30/05