LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 117

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LPC47M192-NW

Manufacturer Part Number
LPC47M192-NW
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of LPC47M192-NW

Lead Free Status / RoHS Status
Compliant

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0x61 in Logical Device A. The PME status bits for the GPIOs are cleared on a write of ‘1’. In addition, the
LPC47M192 provides 19 GPIOs that can directly generate an SMI. See the table in the next section.
7.12.5 GPIO PME AND SMI FUNCTIONALITY
The following GPIOs are dedicated wakeup GPIOs with a status and enable bit in the PME status and enable
registers:
The following PME status and enable registers for these GPIOs:
The following GPIOs can directly generate an SMI and have a status and enable bit in the SMI status and enable
registers.
The following SMI status and enable registers for these GPIOs:
The following GPIOs have “either edge triggered interrupt” (EETI) input capability. These GPIOs can generate a
PME and an SMI on both a high-to-low and a low-to-high edge on the GPIO pin. These GPIOs have a status bit in
the MSC_STS status register that is set on both edges. The corresponding bits in the PME and SMI status registers
are also set on both edges.
The following table summarizes the PME and SMI functionality for each GPIO.
Triggered Interrupt (EETI) input capability for the GPIOs and the power source for the buffer on the I/O pads.
Note 1: GP35 and GP53 have the IRTX function and their output buffers are powered by VTR so that the
SMSC DS – LPC47M192
GP10-GP17
GP20-GP22, GP24-GP26
GP27
GP30, GP31
GP32, GP33
GP34
GP35
GP36, GP37
GP40
GP41
GP42
GP43
GP50-GP52
GP53
GP54-GP57
GP60, GP61
pins are always forced low when not used.
GP10-GP17
GP20-GP22, GP24-GP27
GP30-GP33
GP41, GP43
GP50-GP57
GP60, GP61
PME_STS2 and PME_EN2 for GP10-GP17
PME_STS3 and PME_EN3 for GP20-GP22, GP24-GP27
PME_STS4 and PME_EN4 for GP30-GP33, GP41, GP43, GP60 and GP61
PME_STS5 and PME_EN5 for GP50-GP57
GP20-GP22, GP24-GP26
GP30-GP33
GP41, GP42, GP43
GP54-GP57
GP60, GP61
SMI_STS3 and SMI_EN3 for GP20-GP22, GP24-GP26 and GP60
SMI_STS4 and SMI_EN4 for GP30-GP33, GP41, GP42, GP43 and GP61
SMI_STS5 and SMI_EN5 for GP54-GP57, FAN_TACH1 and FAN_TACH2.
GP21, GP22
GP41, GP43
GP60, GP61
GPIO
nIO_PME
PME
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
DATASHEET
nIO_SMI
Page 117
SMI
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
GP21, GP22
EETI
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
Buffer Power
It also shows the Either Edge
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VTR
VCC
VCC
VCC
VTR
VTR
VTR
Notes
4, 6
1, 5
3, 4
4
4
4
4
5
1
2
2
4
4
4
Rev. 03/30/05

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