LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 170

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LPC47M192-NW

Manufacturer Part Number
LPC47M192-NW
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of LPC47M192-NW

Lead Free Status / RoHS Status
Compliant

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9.3 Chip Level (Global) Control/Configuration Registers [0x00-0x2F]
The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of the
ADDRESS Port for register selection. All unimplemented registers and bits ignore writes and return zero when read.
The INDEX PORT is used to select a configuration register in the chip. The DATA PORT is then used to access the
selected register. These registers are accessible only in the Configuration Mode.
SMSC DS – LPC47M192
Config Control
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
Logical Device #
Default = 0x00
on VCC POR,
VTR POR,
SOFT RESET and
PCI RESET
Card
Reserved
Device ID -
Hard wired
Default = 0x60
on VCC POR,
VTR POR,
SOFT RESET and
PCI RESET
Device Rev
Hard wired
= Current Revision
PowerControl
Default = 0x00
on VCC POR,
VTR POR,
SOFT RESET and
PCI RESET
REGISTER
Level
0x08 - 0x1F Reserved - Writes are ignored, reads return 0 .
0x03 - 0x06 Reserved - Writes are ignored, reads return 0 .
ADDRESS
0x07 R/W
0x22 R/W
0x02 W
0x20 R
0x21 R
0x00 -
0x01
Chip (Global) Control Registers
Table 65 - Chip Level Registers
Chip Level, SMSC Defined
DATASHEET
Reserved - Writes are ignored, reads return 0.
The hardware automatically clears this bit after the
write, there is no need for software to clear the bits.
Bit 0 = 1: Soft Reset. Refer to the “Configuration
Registers” table for the soft reset value for each
register.
A write to this register selects the current logical
device.
configuration registers for each logical device.
Note: The Activate command operates only on the
selected logical device.
A read only register which provides device
identification. Bits[7:0] = 0x60 when read.
A read only register which provides device revision
information. Bits[7:0] = current revision when read.
Bit[0] FDC Power
Bit[1] Reserved
Bit[2] Game Port Power
Bit[3] Parallel Port Power
Bit[4] Serial Port 1 Power
Bit[5] Serial Port 2 Power
Bit[6] MPU-401 Power
Bit[7] Reserved
0: Power Off or Disabled
1: Power On or Enabled
Page 170
This allows access to the control and
DESCRIPTION
Rev. 03/30/05

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