LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 150

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

SMSC DS – LPC47M192
SMI_EN5
Default = 0x00
N/A
MSC_STS
Default = 0x00
N/A
on VTR POR
on VTR POR
NAME
REG OFFSET
(R/W)
(R/W)
(hex)
(R)
(R)
1C
1D
1A
1B
DATASHEET
SMI Enable Register 5
This register is used to enable the different interrupt
sources onto the group nSMI output.
1=Enable
0=Disable
Bit[0] GP54
Bit[1] GP55
Bit[2] GP56
Bit[3] GP57
Bit[4] Reserved
Bit[5] Reserved
Bit[6] FAN_TACH1
Bit[7] FAN_TACH2
Bits[7:0] Reserved – reads return 0
Miscellaneous Status Register
Bits[5:0] can be cleared by writing a 1 to their position
(writing a 0 has no effect).
Bit[0] Either Edge Triggered Interrupt Input 0 Status.
This bit is set when an edge occurs on the GP21 pin.
Bit[1] Either Edge Triggered Interrupt Input 1 Status.
This bit is set when an edge occurs on the GP22 pin.
Bit[2] Either Edge Triggered Interrupt Input 2 Status.
This bit is set when an edge occurs on the GP41 pin.
Bit[3] Either Edge Triggered Interrupt Input 3 Status.
This bit is set when an edge occurs on the GP43 pin.
Bit[4] Either Edge Triggered Interrupt Input 4 Status.
This bit is set when an edge occurs on the GP60 pin.
Bit[5] Either Edge Triggered Interrupt Input 5 Status.
This bit is set when an edge occurs on the GP61 pin.
Bit[7:6] Reserved. This bit always returns zero.
Bits[7:0] Reserved – reads return 0
Page 150
DESCRIPTION
Rev. 03/30/05