LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 67

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt
Identification Register (refer to Interrupt Control Table). When the CPU accesses the IIR, the Serial Port freezes all
interrupts and indicates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial
Port records new interrupts, the current indication does not change until access is completed. The contents of the IIR
are described below.
Bit 0
This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending.
When bit 0 is a logic “0”, an interrupt is pending and the contents of the IIR may be used as a pointer to the
appropriate internal service routine. When bit 0 is a logic “1”, no interrupt is pending.
Bits 1 and 2
These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the Interrupt Control
Table.
Bit 3
In non-FIFO mode, this bit is a logic “0”. In FIFO mode this bit is set along with bit 2 when a timeout interrupt is
pending.
Bits 4 and 5
These bits of the IIR are always logic “0”.
Bits 6 and 7
These two bits are set when the FIFO CONTROL Register bit 0 equals 1.
SMSC DS – LPC47M192
MODE
ONLY
BIT 3
FIFO
0
0
0
1
BIT 2
IDENTIFICATION
0
1
1
1
INTERRUPT
REGISTER
BIT 1
0
1
0
0
BIT 0
1
0
0
0
Bit 7
0
0
1
1
Table 29 – Interrupt Control Table
Y LEVEL
PRIORIT
Highest
Second
Second
DATASHEET
-
Bit 6
0
1
0
1
INTERRUPT SET AND RESET FUNCTIONS
Trigger Level (BYTES)
Received Data
Receiver Line
INTERRUPT
Page 67
Character
Indication
Available
Timeout
Status
TYPE
None
RCVR FIFO
14
1
4
8
Removed From or
there is at least 1
Framing Error or
during the last 4
char in it during
Char times and
Break Interrupt
Overrun Error,
Receiver Data
No Characters
INTERRUPT
Parity Error,
RCVR FIFO
Have Been
Input to the
SOURCE
Available
this time
None
Buffer or the FIFO
Reading the Line
drops below the
Status Register
Receiver Buffer
Read Receiver
INTERRUPT
trigger level.
Reading the
CONTROL
Register
RESET
-
Rev. 03/30/05