LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 84

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

(1) = Compatible Mode
(3) = High Speed Mode
Note:
IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. This document is
available from Microsoft.
7.8.1 IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES
DATA PORT
ADDRESS OFFSET = 00H
The Data Port is located at an offset of ‘00H’ from the base address. The data register is cleared at initialization by
RESET. During a WRITE operation, the Data Register latches the contents of the internal data bus. The contents of
this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation in SPP
mode, PD0 - PD7 ports are buffered (not latched) and output to the host CPU.
STATUS PORT
ADDRESS OFFSET = 01H
The Status Port is located at an offset of ‘01H’ from the base address. The contents of this register are latched for
the duration of a read cycle. The bits of the Status Port are defined as follows:
BIT 0 TMOUT - TIME OUT
This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A logic O
means that no time out error has occurred; a logic 1 means that a time out error has been detected. This bit is
cleared by a RESET. If the TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode Register 2, 0xF1 in Logical Device
3 Configuration Registers) is ‘0’, writing a one to this bit clears the TMOUT status bit. Writing a zero to this bit has no
effect. If the TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode Register 2, 0xF1 in Logical Device 3
Configuration Registers) is ‘1’, the TMOUT bit is cleared on the trailing edge of a read of the EPP Status Register.
BITS 1, 2 -
level.
BIT 3 nERR – nERROR
The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic 0 means an error
has been detected; a logic 1 means no error has been detected.
BIT 4 SLT - PRINTER SELECTED STATUS
The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic 1 means the printer is
on line; a logic 0 means it is not selected.
BIT 5 PE - PAPER END
The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic 1 indicates a paper end;
a logic 0 indicates the presence of paper.
SMSC DS – LPC47M192
CONNECTOR
For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the
are not implemented as register bits, during a read of the Printer Status Register these bits are a low
HOST
12
13
14
15
16
17
PIN NUMBER
78
77
82
81
66
67
DATASHEET
PE
SLCT
nALF
nERROR
nINIT
nSLCTIN
STANDARD
Page 84
(User Defined)
(User Defined)
nDatastb
(User Defined)
nRESET
nAddrstrb
EPP
PError,
nAckReverse (3)
Select
nAutoFd,
HostAck(3)
nFault (1)
nPeriphRequest (3)
nInit(1)
nReverseRqst(3)
nSelectIn(1,3)
ECP
Rev. 03/30/05