LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 14

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

SMSC DS – LPC47M192
QFP PIN#
84
85
87
88
89
86
RXD1
TXD1
nRTS1
nCTS1
nDTR1
nDSR1
NAME
Receiver serial data input for port 1.
Transmit serial data output for port 1.
Active low Request to Send outputs for the
Serial Port. Handshake output signal notifies
modem that the UART is ready to transmit
data. This signal can be programmed by
writing to bit 1 of the Modem Control
Register (MCR).
reset the nRTS signal to inactive mode
(high). nRTS is forced inactive during loop
mode operation.
Active low Clear to Send inputs for the serial
port. Handshake signal which notifies the
UART that the modem is ready to receive
data. The CPU can monitor the status of
nCTS signal by reading bit 4 of Modem
Status Register (MSR). A nCTS signal state
change from low to high after the last MSR
read will set MSR bit 0 to a 1. If bit 3 of the
Interrupt Enable Register is set, the interrupt
is generated when nCTS changes state.
The nCTS signal has no effect on the
transmitter.
Note: Bit 4 of MSR is the complement of
nCTS.
Active low Data Terminal Ready outputs for
the serial port.
notifies modem that the UART is ready to
establish data communication link. This
signal can be programmed by writing to bit 0
of Modem Control Register (MCR). The
hardware reset will reset the nDTR signal to
inactive mode (high).
inactive during loop mode operation.
Active low Data Set Ready input for the
serial port. Handshake signal which notifies
the UART that the modem is ready to
establish the communication link. The CPU
can monitor the status of nDSR signal by
reading bit 5 of Modem Status Register
(MSR). A nDSR signal state change from
low to high after the last MSR read will set
MSR bit 1 to a 1. If bit 3 of Interrupt Enable
Register is set, the interrupt is generated
when nDSR changes state.
Note: Bit 5 of MSR is the complement of
nDSR.
SERIAL PORT 1 INTERFACE (8)
DATASHEET
DESCRIPTION
Handshake output signal
The hardware reset will
Page 14
nDTR is forced
IS
O12
O8
I
O6
I
BUFFER
NAME
VCC
VCC
VCC
VCC
VCC
VCC
WELL
PWR
NOTES
Rev. 03/30/05