LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 73

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received data
available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt.
FIFO POLLED MODE OPERATION
With FCR bit 0 = “1” resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of operation.
Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled mode of operation.
In this mode, the user’s program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO
Polled Mode are as follows:
There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the RCVR and
XMIT FIFOs are still fully capable of holding characters.
Note
Note
SMSC DS – LPC47M192
1
2
: The percentage error for all baud rates, except where indicated otherwise, is 0.2%.
: The High Speed bit is located in the Device Configuration Space.
Bit 0=1 as long as there is one byte in the RCVR FIFO.
Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as when
in the interrupt mode, the IIR is not affected since EIR bit 2=0.
Bit 5 indicates when the XMIT FIFO is empty.
Bit 6 indicates that both the XMIT FIFO and shift register are empty.
Bit 7 indicates whether there are any errors in the RCVR FIFO.
BAUD RATE
Interrupt Enable Register
Interrupt Identification Reg.
FIFO Control
Line Control Reg.
MODEM Control Reg.
Line Status Reg.
MODEM Status Reg.
DESIRED
115200
230400
460800
19200
38400
57600
134.5
1200
1800
2000
2400
3600
4800
7200
9600
110
150
300
600
50
75
REGISTER/SIGNAL
GENERATE 16X CLOCK
DIVISOR USED TO
32770
32769
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
1
RESET
RESET
RESET
RESET
RESET
RESET
RESET
Table 31 - Reset Function Table
DATASHEET
RESET CONTROL
Table 30 - Baud Rates
Page 73
BETWEEN DESIRED AND ACTUAL
PERCENT ERROR DIFFERENCE
0.001
0.004
0.005
0.030
0.16
0.16
0.16
0.16
All bits low
Bit 0 is high; Bits 1 - 7 low
All bits low
All bits low
All bits low
All bits low except 5, 6 high
Bits 0 - 3 low; Bits 4 - 7 input
-
-
-
-
-
-
-
-
-
-
-
-
-
RESET STATE
1
SPEED BIT
HIGH
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
Rev. 03/30/05
2