LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 110

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program control. This signal
is AND’ed together externally with the reset signal (nKBDRST) from the keyboard controller to provide a software
means of resetting the CPU. This provides a faster means of reset than is provided by the keyboard controller.
Writing a 1 to bit 0 in the Port 92 Register causes this signal to pulse low for a minimum of 6µs, after a delay of a
minimum of 14µs. Before another nALT_RST pulse can be generated, bit 0 must be set to 0 either by a system reset
of a write to Port 92. Upon reset, this signal is driven inactive high (bit 0 in the Port 92 Register is set to 0).
If Port 92 is enabled, i.e., bit 2 of KRST_GA20 is set to 1, then a pulse is generated by writing a 1 to bit 0 of the Port
92 Register and this pulse is AND’ed with the pulse generated from the 8042. This pulse is output on pin KRESET
and its polarity is controlled by the GPI/O polarity configuration.
Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support of real mode compatible
software. This signal is externally OR’ed with the A20GATE signal from the keyboard controller and CPURST to
control the nA20M input of the CPU. Writing a 0 to bit 1 of the Port 92 Register forces ALT_A20 low. ALT_A20 low
drives nA20M to the CPU low, if A20GATE from the keyboard controller is also low. Writing a 1 to bit 1 of the Port 92
Register forces ALT_A20 high. ALT_A20 high drives nA20M to the CPU high, regardless of the state of A20GATE
from the keyboard controller. Upon reset, this signal is driven low.
SMSC DS – LPC47M192
Note: When Port 92 is
writes are ignored and
return undefined
P92
8042
Bit 0
P20
Pulse
Gen
14us
~ ~
KRST_GA2
8042
P21
0
0
1
1
DATASHEET
Bit 2
nGATEA20
ALT_A20
6us
14us
~ ~
Page 110
0
1
0
1
KRST
nALT RST
6us
System
nA20M
0
1
1
1
KBDRS
Rev. 03/30/05