LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 188

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

SMSC DS – LPC47M192
NAME/DEFAULT
VID Register
Default:
Bits[7:4]=0000
Bits[3:0]=VID3-
VID0 on HVCC
POR
Initialization
VID4 Register
Default:
Bits[7]=1,
Bits[6:1]=0
Bit[0]=VID4
HVCC POR and
Initialization
Test
Register
Default = 0x00
on HVCC POR
and Initialization
Error
Register
Default = 0x00
on HVCC POR
and Initialization
Debug
Mode
and
on
Bit[7] is (R/W)
Bits[6:0] are
REGISTER
Read Only;
OFFSET
(R/W)
(hex)
(R)
(R)
4A
4B
47
49
DATASHEET
Bits[3:0] VID[3:0]
The VID[3:0] inputs from Pentium/PRO power supplies to indicate
the operating voltage (e.g. 1.5V to 2.9V).
Bits[6:4] Reserved
Bit[7] RESET# Enable
0= Enables A0 pin for lowest order programmable bit of SMBus
address (Default)
1= Enables the RESET# pin output function
Bit[0] VID 4
VID 4 Input (If selected).
Bits[6:1] Reserved
Bit[7] Reserved1
Bit[0] selects the ADC test mode. The default for this bit is zero,
which deactivates ADC test mode.
Bit[1] selects the digital test mode. The default for this bit is zero,
which deactivates digital test mode.
Bit[2] selects the external clock test mode. The default for this bit
is zero, which deactivates external oscillator clock test mode.
Bit[3] selects either 8 or 1 averaging for the ADC test mode. The
default for this bit is zero, which sets the averaging to 8 for the
ADC test mode. A one in this bit selects no averaging.
Bit[4] selects the oscillator clock to be muxed out on the VID2 pin.
The default for this bit is zero, which deactivates mux oscillator
clock test mode.
Bits[7:5] are used by the analog block for test purposes. These
three
dig_test_an_pad[2:0]. These bits are also used to mux out either
the SDA line or the SCLK line to the VID3 pin. If bits[7:5] are ‘001’,
then the SDA line is muxed out onto the VID3 pin. If bits[7:5] are
‘010’, then the SCLK line is muxed out onto the VID3 pin.
Bit[0] indicates that no NACK was generated by the host during
either a read byte protocol or a receive byte protocol.
Bit[1] indicates a read or a write was attempted to an invalid
register location.
Bit[2] indicates a write to a read only register was attempted
Bit[3] indicates a receive byte protocol was attempted when the
address pointer register pointed to the 00h location. This is the
default register location on power on reset. As noted in the “Bus
Protocols” section of the “Hardware Monitoring Interface” section,
the Internal Address register should be set up with a valid address
location by either a send byte protocol or a write byte protocol
after power-on-reset, before the receive byte protocol.
Bit[4] indicates an invalid slave address was detected.
Bit[5] indicates a premature stop was detected.
Bit[6] indicates an error was detected during the SMBus Receive
Byte Protocol Response to an ARA.
Bit[7] is reserved.
bits
Page 188
of
register
DESCRIPTION
4Ah
are
muxed
out
on
Rev. 03/30/05
pins