LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 25

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

6.4 32.768 kHz Trickle Clock Input
6.4.1 INDICATION OF 32KHZ CLOCK
Bit[0] (CLK32_PRSN) is defined as follows:
0=32kHz clock is connected to the CLKI32 pin (default)
1=32kHz clock is not connected to the CLKI32 pin (pin is grounded).
Bit 0 controls the source of the 32kHz (nominal) clock for the fan tachometer logic, the LED blink logic and the “wake
on specific key” logic. When the external 32kHz clock is connected, that will be the source for the fan tachometer,
LED and “wake on specific key” logic. When the external 32kHz clock is not connected, an internal 32kHz clock
source will be derived from the 14MHz clock for the fan tachometer, LED and “wake on specific key” logic.
The following functions will not work under VTR power (VCC removed) if the external 32kHz clock is not connected.
These functions will work under VCC power even if the external 32 kHz clock is not connected.
6.5 Internal PWRGOOD
6.6 Maximum Current Values
6.6.1 SUPER I/O FUNCTIONS
SMSC DS – LPC47M192
Other Pins:
-
-
-
-
Fan Tachometer
Wake on specific key
LED blink
The LPC47M192 utilizes a 32.768 kHz trickle input to supply a clock signal for the fan tachometer logic, LED
blink and wake on specific key function.
There is a bit to indicate whether or not the 32kHz clock input is connected to the LPC47M192. This bit is
located at bit 0 of the CLOCKI32 register at 0xF0 in Logical Device A. This register is powered by VTR and
reset on a VTR POR.
An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the host
interface as V
and the LPC47M192 host interface is active. When the internal PWRGOOD signal is “0” (inactive), V
2.3V (nominal), and the LPC47M192 host interface is inactive; that is, LPC bus reads and writes will not be
decoded.
The LPC47M192 device pins IO_PME#, CLOCKI32, KDAT, MDAT, nRI1, nRI2, RXD2 and most GPIOs (as
input) are part of the PME interface and remain active when the internal PWRGOOD signal has gone inactive,
provided V
remain active when the internal PWRGOOD signal has gone inactive, provided V
Power Functionality section. The internal PWRGOOD signal is also used to disable the IR Half Duplex
Timeout.
See the “Operational Description” section for the maximum current values.
The maximum VTR current, I
0V to/from 3.3V. The total maximum current for the part is the unloaded value PLUS the maximum current
sourced by the pin that is driven by VTR. The pins that are powered by VTR are as follows: GP42/nIO_PME,
IRTX2/GP35, GP53/TXD2(IRTX), GP60/LED1, GP61/LED2, and CLKI32. These pins, if configured as push-
pull outputs, will source a minimum of 6mA at 2.4V when driving.
The maximum VCC current, I
0V to/from 3.3V.
IRTX2/GP35 (output, buffer powered by VTR)
GP53/TXD2(IRTX) (output, buffer powered by VTR)
GP60/LED1 (output, buffer powered by VTR)
GP61/LED2 (output, buffer powered by VTR)
TR
cc
is powered. The IRTX2/GP35, GP53/TXD2(IRTX), GP60/LED1 and GP61/LED2 pins also
cycles on and off. When the internal PWRGOOD signal is “1” (active), V
TR
CC
, is given with all outputs open (not loaded), and all inputs transitioning from/to
, is given with all outputs open (not loaded) and all inputs transitioning from/to
DATASHEET
Page 25
TR
is powered. See Trickle
cc
> 2.3V (nominal),
Rev. 03/30/05
cc
<=