LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 142

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

The following registers are located at an offset from (PME_BLK) the address programmed into the base I/O address
register for Logical Device A.
SMSC DS – LPC47M192
PME_STS
Default = 0x00
on VTR POR
N/A
PME_EN
Default = 0x00
on VTR POR
N/A
PME_STS1
Default = 0x00
on VTR POR
NAME
REG OFFSET
Table 63 - Runtime Register Block Description
(R/W)
(R/W)
(R/W)
(hex)
(R)
(R)
00
01
02
03
04
DATASHEET
Bit[0] PME_Status
= 0 (default)
= 1 Set when LPC47M192 would normally assert the
Bit[7:1] Reserved
PME_Status is not affected by Vcc POR, SOFT RESET
or PCI RESET.
Writing a “1” to PME_Status will clear it and cause the
LPC47M192 to stop asserting nIO_PME, in enabled.
Writing a “0” to PME_Status has no effect.
Bits[7:0] Reserved – reads return 0
Bit[0] PME_En
= 0
= 1
Bit[7:1] Reserved
PME_En is not affected by Vcc POR, SOFT RESET or
PCI RESET
Bits[7:0] Reserved – reads return 0
PME Wake Status Register 1
This register indicates the state of the individual PME
wake sources, independent of the individual source
enables or the PME_En bit.
If the wake source has asserted a wake event, the
associated PME Wake Status bit will be a “1”.
Bit[0] Reserved (Note 7)
Bit[1] RI2
Bit[2] RI1
Bit[3] KBD
Bit[4] MOUSE
Bit[5] SPEKEY (Wake on specific key)
Bit[6] FAN_TACH1
Bit[7] FAN_TACH2
The PME Wake Status register is not affected by Vcc
POR, SOFT RESET or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any
bit in PME Wake Status Register has no effect.
Page 142
nIO_PME signal, independent of the state of the
PME_En bit.
nIO_PME signal assertion is disabled (default)
Enables LPC47M192 to assert nIO_PME signal
DESCRIPTION
Rev. 03/30/05