LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 159

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

SMSC DS – LPC47M192
GP43
Default = 0x01
on VTR POR
Bits[3:2] are reset
(cleared)
POR, VTR POR and
PCI Reset
GP50
Default = 0x01
on VTR POR
GP51
Default = 0x01
on VTR POR
NAME
on
VCC
REG OFFSET
(R/W)
(R/W)
(R/W)
(hex)
3E
3F
40
DATASHEET
General Purpose I/0 bit 4.3
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[3:2] Alternate Function Select
11=Either Edge Triggered Interrupt Input 3 (Note 1)
10=Reserved
01=Device Disable Register Control. The GP43 pin is an
input, with non-inverted polarity. When bits[3:2]=01, they
cannot be changed by writing to these bits; they are
cleared by VCC POR, PCI Reset and VTR POR. That is,
when the DDRC function is selected for this pin, it cannot
be changed, except by a VCC POR, PCI Reset or VTR
POR.
00=Basic GPIO function
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/0 bit 5.0
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[3:2] Alternate Function Select
11=Reserved
10=Reserved
01=nRI2 (User Note 1)
00=GPIO
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/0 bit 5.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[3:2] Alternate Function Select
11=Reserved
10=Reserved
01=nDCD2
00=GPIO
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
The Device Disable register is controlled by the value of
the GP43 pin as follows:
If the GP43 pin is high, the Device Disable Register is
If the GP43 pin is low, the Device Disable Register is
Page 159
Read-Only.
Read/Write.
DESCRIPTION
Rev. 03/30/05