LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 132

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

7.18.2.1.5
The device will not time-out when SCLK is held low longer than T
7.18.2.1.6
The Hardware Monitor Block supports stretching of the SCLK by other devices on the SMBus. The Hardware Monitor
Block does not stretch the SCLK.
7.18.2.1.7
The SMBus Slave Interface complies with the SMBus AC Timing Specification. See the SMBus timing in the “Timing
Diagram” section.
7.18.2.1.8
The SMBus Slave Interface will reset and return to the idle state upon a START field followed immediately by a STOP
field.
7.18.2.1.9
The Hardware Monitor Block implements the SMBALERT# signal. The THERM# interrupt pin can be used as the
SMBALERT#. SMBALERT# is used in conjunction with the SMBus General Call Address, 0001 100.
The Hardware Monitor Block device can signal the host that it wants to talk by pulling the SMBALERT# low. The host
processes the interrupt and simultaneously accesses all SMBALERT# devices through a modified Receive Byte
operation with the Alert Response Address (ARA). The Hardware Monitor Block, which pulled SMBALERT# low, will
acknowledge the Alert Response Address and respond with its device address.
The host performs a modified Receive Byte operation with the alert response address. The 7-bit device address
provided by the Hardware Monitor Block device is placed in the 7 most significant bits of the byte. The eighth bit can
be a zero or one.
After acknowledging the slave address, the Hardware Monitor Block must disengage its SMBALERT# pulldown. If the
condition that caused the interrupt remains, the Hardware Monitor Block will reassert the SMBALERT# on the next
monitoring cycle.
7.18.3 HARDWARE MONITORING BLOCK
The following sub-sections describe the Hardware Monitoring Block.
7.18.3.1
The Hardware Monitor Block’s monitoring function is started by writing a ‘1’ to the START bit in the Configuration
Register (0x40). Measured values from the analog inputs and temperature sensors are stored in the Value Registers.
These values can be compared to the programmed limits in the Limit Register via SMBus interface. The out-of-limit
and diode fault conditions are stored in the Interrupt Status Registers.
7.18.3.2
7.18.3.2.1
All the registers in the Hardware Monitor Block reset to a default value when power is applied to the block. The
default state of the register is shown in the table in the Register Summary subsection. The default state of Value or
Limit Registers are not shown because these registers have indeterminate power on values. Usually the first action
after power up is to write limits into the Limit Registers.
SMSC DS – LPC47M192
Input Monitoring
Resetting the Hardware Monitoring Block
FIELD:
Slave Device Time-Out
Stretching the SCLK Signal
SMBus Timing
Bus Reset Sequence
SMBus Alert Response Address
Power On Reset
Bits:
Table 61 - Modified SMBus Receive Byte Protocol Response to ARA
START
1
RESPONSE
ADDRESS
ALERT
7
DATASHEET
RD
1
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ACK
1
TIME-OUT
BLOCK SLAVE
HW MONITOR
ADDRESS
Min = 25ms.
8
NACK
1
STOP
1
Rev. 03/30/05