LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 174

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

Note 1 : A logical device will be active and powered up according to the following equation unless otherwise specified:
DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET).
The Logical device’s Activate Bit and its Pwr/Control Bit are linked such that setting or clearing one sets or clears the
other.
Note 2 : If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical Device I/O
map, then read or write is not valid and is ignored.
Note 3 : The default value of the Primary Interrupt Select register for logical device 0 is 0x06.
Note 4 : The default value of the DMA Channel Select register for logical device 0 (FDD) is 0x02 and for logical device
3 and 5 is 0x04.
SMSC DS – LPC47M192
DMA Channel Select
Default = 0x02 or 0x04
(Note 4)
on VCC POR, VTR POR,
PCI RESET and
SOFT RESET
32-Bit
Configuration
Logical Device
Logical
Configuration
Reserved
LOGICAL DEVICE
REGISTER
Memory
Device
Space
(0xA9-0xDF)
(0xE0-0xFE)
(0x76-0xA8)
(0x74,0x75)
ADDRESS
DATASHEET
0xFF
Page 174
Only 0x74 is implemented for FDC and Parallel
port.
writes and returns zero when read. Refer to
DMA Channel Configuration.
Reserved - not implemented. These register
locations ignore writes and return zero when
read.
Reserved - not implemented. These register
locations ignore writes and return zero when
read.
Reserved – Vendor Defined (see SMSC
defined
Registers).
Reserved
0x75 is not implemented and ignores
Logical
DESCRIPTION
Device
Configuration
Rev. 03/30/05