LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 114

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

PIN#
100
28
92
94
95
96
97
98
99
48
49
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
7.12.2 DESCRIPTION
Each GPIO port has a 1-bit data register and an 8-bit configuration control register. The data register for each GPIO
port is represented as a bit in one of the 8-bit GPIO DATA Registers, GP1 to GP6. The bits in these registers reflect
the value of the associated GPIO pin as follows. Pin is an input: The bit is the value of the GPIO pin. Pin is an
output: The value written to the bit goes to the GPIO pin. Latched on read and write. All of the GPIO registers are
located in the PME block see “Run Time Register” section. The GPIO ports with their alternate functions and
configuration state register addresses are listed in Table 53.
SMSC DS – LPC47M192
PIN#
QFP
N/A
32
33
34
35
36
37
38
39
41
42
43
45
46
47
GP43/DDRC
GP50/nRI2
GP51/nDCD2
GP52/RXD2(IRRX)
GP53/TXD2 (IRTX)
GP54/nDSR2
GP55/nRTS2
GP56/nCTS2
GP57/nDTR2
GP60/LED1
GP61/LED2
Alternate Funcs)
(Default Func/
PIN NAME
FUNCTION
DEFAULT
Reserved
These pins are inputs to VCC and VTR powered logic.
The fan control pins (FAN1 and FAN2) come up as outputs and low following a VCC POR and PCI Reset.
The IRTX pins (IRTX2/GP35 and GP53/TXD2(IRTX)) are driven low when the part is powered by VTR
(VCC=0V with VTR=3.3V). These pins will remain low following a VCC POR until IRTX function is selected
by setting the activate bit, at which time the pin will reflect the state of the transmit output of the IR block. It
will remain low following a VCC POR until GPIO input function is selected, at which time the pin will reflect
the state of the GPIO data bit. The GP53/TXD2 (IRTX) pin will remain low following a VCC POR (in
addition to conditions stated above) until serial port 2 is enabled by setting the activate bit, at which time
the pin will reflect the state of the transmit output of the Serial Port 2 block.
These pins are inputs to VCC powered logic.
Bits [3:2] (Alternate Function Select bits) of this register are reset (cleared) on VCC POR and PCI Reset
(and VTR POR).
(System
Option)
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO PIN
WELL
PWR
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VTR
VTR
VTR
Joystick 1 Button 1
Joystick 1 Button 2
Joystick 2 Button 1
Joystick 2 Button 2
Joystick 1 X-Axis
Joystick 1 Y-Axis
Joystick 2 X-Axis
Joystick 2 Y-Axis
ALT. FUNC. 1
MIDI_OUT
MIDI_IN
Out – low
RESET
P17
P16
P12
Table 53 - General Purpose I/O Port Assignments
PCI
In
-
-
-
-
-
-
-
-
-
VCC
POR
Out–
low
In
-
-
-
-
-
-
-
-
-
DATASHEET
POR
Out–
VTR
FUNC. 2
low
In
In
In
In
In
In
In
In
In
In
ALT.
EETI
EETI
OFFS
(hex)
Page 114
REG
ET
3E
3F
40
41
42
43
44
45
46
47
48
FUNC. 3
GP43
GP50
GP51
GP52
GP53
GP54
GP55
GP56
GP57
GP60
GP61
REG
ALT.
RESET
GPIO REGISTER
Note 5
0x00
PCI
-
-
-
-
-
-
-
-
-
REGISTER
DATA
POR
0x00
VCC
Note
GP1
GP2
5
-
-
-
-
-
-
-
-
-
POR
0x01
0x01
0x01
0x01
0x00
0x01
0x01
0x01
0x01
0x01
0x01
VTR
1
REGISTER
BIT NO.
DATA
RESET
SOFT
0
1
2
3
4
5
6
0
1
2
3
5
7
4
6
-
-
-
-
-
-
-
-
-
-
-
SMI/PME
SMI/PME
SMI/PME
SMI/PME
SMI/PME
SMI/PME
SMI/PME
SMI/PME
REGISTER
PME
PME
PME
PME
OFFSET
Rev. 03/30/05
(HEX)
4B
4C
NOTES
1, 5
1, 3
1
1
1
1
1
1
1
1
1