LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 119

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

enabled onto the serial IRQ stream (IRQ2) via Bit[6] in the SMI Enable Register 2. The internal SMI can also be
enabled onto the nIO_PME pin. Bit[5] of the SMI Enable Register 2 is used to enable the SMI output onto the
nIO_PME pin (GP42). This bit will enable the internal SMI output into the PME logic through the DEVINT_STS bit in
PME_STS3. See PME section for more details.
An example logic equation for the nSMI output for SMI registers 1 and 2 is as follows:
nSMI = (EN_PINT and IRQ_PINT) or (EN_U2INT and IRQ_U2INT) or (EN_U1INT and IRQ_U1INT) or (EN_FINT and
IRQ_FINT) or (EN_MPU401 and IRQ_MPU401) or (EN_MINT and IRQ_MINT) or (EN_KINT and IRQ_KINT) or
(EN_IRINT and IRQ_IRINT) or ENP12 and IRQ_P12)
Note: The prefixes EN and IRQ are used above to indicate SMI enable bit and SMI status bit respectively.
7.13.1 SMI REGISTERS
The SMI event bits for the GPIOs and the Fan tachometer events are located in the SMI status and Enable registers
3-5. The polarity of the edge used to set the status bit and generate an SMI is controlled by the polarity bit of the
control registers. For non-inverted polarity (default) the status bit is set on the low-to-high edge. If the EETI function
is selected for a GPIO then both a high-to-low and a low-to-high edge will set the corresponding SMI status bit.
Status bits for the GPIOs are cleared on a write of ‘1’.
The SMI logic for these events is implemented such that the output of the status bit for each event is combined with
the corresponding enable bit in order to generate an SMI.
The SMI registers are accessed at an offset from PME_BLK (see “Runtime Registers” section for more information).
The SMI event bits for the super I/O devices are located in the SMI status and enable register 1 and 2. All of these
status bits are cleared at the source except for IRINT, which is cleared by a read of the SMI_STS2 register; these
status bits are not cleared by a write of ‘1’. The SMI logic for these events is implemented such that each event is
directly combined with the corresponding enable bit in order to generate an SMI.
See the “Runtime Registers” section for the definition of these registers.
7.14 PME SUPPORT
The LPC47M192 offers support for power management events (PMEs), also referred to as a System Control Interrupt
(SCI) events in an ACPI system. A power management event is indicated to the chipset via the assertion of the
nIO_PME signal. In the LPC47M192, the nIO_PME is asserted by active transitions on the ring indicator inputs nRI1
and nRI2, valid NEC infrared remote control frames, active keyboard-data edges, active mouse-data edges,
programmable edges on GPIO pins and fan tachometer event. The GP42/nIO_PME pin, when selected for the
nIO_PME function, can be programmed to be active high or active low via the polarity bit in the GP42 register. The
output buffer type of the pin can be programmed to be open-drain or push-pull via bit 7 of the GP42 register. The
nIO_PME pin function defaults to active low, open-drain output.
Note: If the nRI2 pin is used for wakeup, the inactive state of the TXD2 pin may need to be changed. See the IR
Transmit Pin section.
The PME functionality is controlled by the PME status and enable registers in the runtime registers block, which is
located at the address programmed in configuration registers 0x60 and 0x61 in Logical Device A. The PME Enable
bit, PME_EN, globally controls PME Wake-up events. When PME_EN is inactive, the nIO_PME signal can not be
asserted. When PME_EN is asserted, any wake source whose individual PME Wake Enable register bit is asserted
can cause nIO_PME to become asserted.
The PME Status register indicates that an enabled wake source has occurred, and if the PME_EN bit is set, asserted
the nIO_PME signal. The PME Status bit is asserted by active transitions of PME wake sources. PME_Status will
become asserted independent of the state of the global PME enable bit, PME_EN.
The following pertains to the PME status bits for each event:
SMSC DS – LPC47M192
The output of the status bit for each event is combined with the corresponding enable bit to set the PME status
bit.
The status bit for any pending events must be cleared in order to clear the PME_STS bit. Status bits are cleared
on a write of ‘1’.
DATASHEET
Page 119
Rev. 03/30/05