LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 24

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

Note: The Fan Tachometers can generate a PME when VCC=0. Clear the enable bits for the fan tachometers
before removing fan power.
The following requirements apply to all I/O pins that are specified to be 5 volt tolerant.
The GPIOs that are used for PME wakeup as input are GP10-GP17, GP20-GP22, GP24-GP27, GP30-GP33, GP41,
GP43, GP50-GP57, GP60, GP61. These GPIOs function as follows (with the exception of GP53, GP60 and GP61 -
see below):
All GPIOs listed above are for PME wakeup as a GPIO (or alternate function). Note that GP32 and GP33 cannot be
used for wakeup under VTR power (VCC=0) since these are the fan control pins which come up as outputs and low
following a VCC POR and PCI Reset. GP53 cannot be used for wakeup under VTR power since this is the IRTX pin
which comes up as output and low following a VTR POR, a VCC POR and PCI Reset. GP43 reverts to the basic
GPIO function when VCC is removed from the part, but its programmed input/output, invert/non-invert and output
buffer type is retained.
The other GPIOs function as follows:
GP34, GP36, GP37 and GP40:
GP35, GP42, GP53, GP60 and GP61:
The IRTX pins (IRTX2/GP35 and GP53/TXD2(IRTX)) are powered by VTR so that they are driven low when VCC =
0V with VTR = 3.3V. These pins will remain low following a VCC POR until serial port 2 is enabled by setting the
activate bit, at which time the pin will reflect the state of the transmit output of the Serial Port 2 block.
The following list summarizes the blocks, registers and pins that are powered by VTR:
SMSC DS – LPC47M192
Fan Tachometers (Note)
GPIOs for wakeup. See below.
I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0), these pins may
only be configured as inputs. These pins have input buffers into the wakeup logic that are powered by VTR.
I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0), are powered by
VTR. This means, at a minimum, they will source their specified current from VTR even when VCC is present.
Buffers are powered by VCC, but in the absence of VCC they are backdrive protected (they do not impose a load
on any external VTR powered circuitry). They are wakeup compatible as inputs under VTR power. These pins
have input buffers into the wakeup logic that are powered by VTR.
Buffers are powered by VCC. In the absence of VCC they are backdrive protected. These pins do not have input
buffers into the wakeup logic that are powered by VTR, and are not used for wakeup.
Buffers powered by VTR. GP35 and GP53 have IRTX as the alternate function and their output buffers are
powered by VTR so that the pins are always forced low when not used. GP35 and GP53 cannot be used for
wakeup. GP42 is the nIO_PME pin which is active under VTR. GP60 and GP61 have LED as the alternate
function and the logic is able to control the pin under VTR.
PME interface block
PME runtime register block (includes all PME, SMI, GPIO, Fan and other miscellaneous registers)
“Wake on Specific Key” logic
LED control logic
Fan Tachometers
Pins for PME Wakeup:
-
-
-
-
-
-
GP42/nIO_PME (output, buffer powered by VTR)
nRI1 (input)
GP50/nRI2 (input)
KDAT (input)
MDAT (input)
GPIOs (GP10-GP17, GP20-GP22, GP24-GP27, GP30-GP33, GP41, GP43, GP50-GP57, GP60, GP61) – all
input-only except GP53, GP60, GP61. See below.
DATASHEET
Page 24
Rev. 03/30/05