LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 32

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

BIT 4 nTRACK 0
Active low status of the TRK0 disk interface input.
BIT 5 STEP
Active high status of the STEP output disk interface output pin.
BIT 6 nDRV2
This function is not supported. This bit is always read as “1”.
BIT 7 INTERRUPT PENDING
Active high bit indicating the state of the Floppy Disk Interrupt output.
PS/2 Model 30 Mode
BIT 0 DIRECTION
Active low status indicating the direction of head movement. A logic “0” indicates inward direction; a logic “1” indicates
outward direction.
BIT 1 WRITE PROTECT
Active high status of the WRITE PROTECT disk interface input. A logic “1” indicates that the disk is write protected.
BIT 2 INDEX
Active high status of the INDEX disk interface input.
BIT 3 HEAD SELECT
Active low status of the HDSEL disk interface input. A logic “0” selects side 1 and a logic “1” selects side 0.
BIT 4 TRACK 0
Active high status of the TRK0 disk interface input.
BIT 5 STEP
Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active,
and is cleared with a read from the DIR register, or with a hardware reset or software reset.
BIT 6 DMA REQUEST
Active high status of the DMA request pending.
BIT 7 INTERRUPT PENDING
Active high bit indicating the state of the Floppy Disk Interrupt.
STATUS REGISTER B (SRB)
Address 3F1 READ ONLY
This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30 modes. The
SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 – D7 are held in a
high impedance state for a read of address 3F1.
PS/2 Mode
SMSC DS – LPC47M192
RESET
RESET
COND.
COND.
PENDING
INT
7
1
1
7
0
DRQ
6
1
1
6
0
DATASHEET
STEP
F/F
DRIVE
SEL0
5
0
5
0
TRK0 nHDSEL
N/A
Page 32
TOGGLE
4
WDATA
4
0
3
1
TOGGLE
RDATA
3
0
INDX
N/A
2
WGATE
2
0
N/A
WP
1
MOT
EN1
nDIR
1
0
0
1
MOT
EN0
0
0
Rev. 03/30/05