LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 106

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

7.11.1 KEYBOARD INTERFACE
The LPC47M192 LPC interface is functionally compatible with the 8042 style host interface. It consists of the D0-7
data signals; the read and write signals and the Status register, Input Data register, and Output Data register. Table
49 shows how the interface decodes the control signals. In addition to the above signals, the host interface includes
keyboard and mouse IRQs.
Note 1: These registers consist of three separate 8 bit registers. Status, Data/Command Write and Data Read.
Keyboard Data Write
This is an 8 bit write only register. When written, the C/D status bit of the status register is cleared to zero and the
IBF bit is set.
Keyboard Data Read
This is an 8 bit read only register. If enabled by “ENABLE FLAGS”, when read, the KIRQ output is cleared and the
OBF flag in the status register is cleared. If not enabled, the KIRQ and/or AUXOBF1 must be cleared in software.
Keyboard Command Write
This is an 8 bit write only register. When written, the C/D status bit of the status register is set to one and the IBF bit
is set.
Keyboard Status Read
This is an 8 bit read only register. Refer to the description of the Status Register for more information.
CPU-to-Host Communication
The LPC47M192 CPU can write to the Output Data register via register DBB. A write to this register automatically
sets Bit 0 (OBF) in the Status register. See Table 50.
Host-to-CPU Communication
The host system can send both commands and data to the Input Data register. The CPU differentiates between
commands and data by reading the value of Bit 3 of the Status register. When bit 3 is “1”, the CPU interprets the
register contents as a command. When bit 3 is “0”, the CPU interprets the register contents as data. During a host
write operation, bit 3 is set to “1” if SA2 = 1 or reset to “0” if SA2 = 0.
SMSC DS – LPC47M192
OUT DBB
8042 INSTRUCTION
ADDRESS
0x60
0x64
Command
Write
Read
Write
Read
Set OBF, and, if enabled, the KIRQ output signal goes high
Table 50 – Host Interface Flags
Table 49 - I/O Address Map
DATASHEET
BLOCK
KDATA
KDATA
KDCTL
KDCTL
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Keyboard Data Write (C/D=0)
Keyboard Data Read
Keyboard Command Write (C/D=1)
Keyboard Status Read
FLAG
FUNCTION (NOTE 1)
Rev. 03/30/05