LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 129

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

7.18 Hardware Monitoring Interface
The Hardware Monitoring Block is a standalone block in the 2. It can be accessed using SMBus interface. This block
is used to monitor +1.5, +1.8, +2.5V, +3.3V, +5V, +12V and Vccp (core processor) voltages. It can also monitor its
own internal HVCC or HVSB. The block can be used to measure internal temperature and two external temperatures
and diode faults. It can indicate out-of-limit temperature and voltage conditions. The block has an ability to output
20ms low pulse.
7.18.1 HARDWARE MONITORING INTERFACE SIGNAL DEFINITION
The following table shows the pins required for the Hardware Monitoring Block.
7.18.2 SMBUS INTERFACE
The host processor communicates with the Hardware Monitor Block through a series of read/write registers via the
SMBus interface. SMBus is a serial communication protocol between a computer host and its peripheral devices.
The SMBus protocol includes a physical layer based on the I
SMSC DS – LPC47M192
THERM#/XNOR_OUT
D0-/XNOR_IN
12V_IN/VID4
A0/RESET#/
PIN NAME
+Vccp_IN
+3.3V_IN
+2.5V_IN
+1.8V_IN
+1.5V_IN
+5V_IN
HVCC
HVSS
SCLK
VID0
VID1
VID2
VID3
SDA
D0+
D1+
D1-
Digital I/O
(Open Drain)
Digital Input
Analog Ground
Power
Digital Input
Digital Input
Digital Input
Digital Input
Analog Input/
Digital Input
Analog Input
Analog Input
Analog Input
Analog
Digital Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Digital I/O
(Open Drain)
TYPE
Input/
DATASHEET
System Management Bus bi-directional Data.
output.
System Management Bus Clock.
Internally connected to all of the Hardware Monitoring Block
circuitry.
+3.3V VCC pin dedicated to the Hardware Monitoring block.
Can be powered by +3.3V Standby power if monitoring in low
power states is required.
Voltage supply readout from the processor. This value is read
in the VID Register.
Voltage supply readout from the processor. This value is read
in the VID Register.
Voltage supply readout from the processor. This value is read
in the VID Register.
Voltage supply readout from the processor. This value is read
in the VID Register.
This is the negative input (current sink) from the remote
thermal diode. This serves as the negative input into the A/D.
If held high at power-up, initiates XNOR chain test mode.
This is the positive input (current source) from the remote
thermal diode. This serves as the positive input into the A/D.
See D0- pin description.
See D0+ description.
Defaults to Analog Input for +12V. Optionally, can be
configured to read the VID4 pin, a voltage supply readout from
the processor. This value is read in the VID4 Register.
Analog input for +5V
Analog input for +3.3V
Analog input for +2.5V
Analog input for +1.8V
Analog input for +1.5V
Analog input for +Vccp (processor voltage: 0 to 3.0V).
The lowest order programmable bit of the SMBus Address.
Can also be configured to be a minimum 20msec low Reset
output pulse, or as an interrupt output for temperature and
voltage interrupts. This pin functions as an output when the
Hardware Monitor Block is in XNOR-Chain test mode.
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C
TM
serial bus.
DESCRIPTION
Open Drain
Rev. 03/30/05