LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 219

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

SMBus Timing
Note 1: The SMBus timing (e.g., max clock frequency of 400kHz) specified exceeds that specified in the System
Note 2: At 400kHz, spikes of a maximum pulse width of 50ns must be suppressed by the input filter.
Note 3: If using 100 kHz clock frequency, the next data bit output to the SDA line will be 1250 ns (1000 ns (T
SMSC DS – LPC47M192
SDA
SCLK
F
T
T
T
T
T
T
T
T
T
T
T
C
SYMBOL
Management Bus Specification, Rev 1.1. This corresponds to the maximum clock frequency for fast mode
devices on the I
+ 250 ns (T
SMB
SP
BUF
SU
SU
SU
HD
HD
LOW
HIGH
F
R
b
P
:
:
:
:
:
STA
STO
DAT
STA
DAT
t
BUF
S
SU
Spike Suppression
Condition
Condition. After this period, the first
clock is generated.
SMB Operating Frequency
Bus free time between Stop and Start
Hold time after (Repeated) Start
Repeated Start Condition setup time
Stop Condition setup time
Data hold time
Data setup time
Clock low period
Clock high period
Clock/Data Fall Time
Clock/Data Rise Time
Capacitive load for each bus line
:
DAT
t
2
HD;STA
C bus. See “The I
t
LOW
min) @ 100 kHz) before the SCLK line is released.
t
HD;DAT
PARAMETER
t
R
FIGURE 44 – SMBUS TIMING
2
C Bus Specification,” version 2.0, Dec. 1998.
DATASHEET
t
HIGH
Page 219
t
SU;DAT
t
F
t
20+0.1C
20+0.1C
SU;STA
MIN
100
1.3
0.6
0.6
0.6
0.3
1.3
0.6
10
LIMITS
b
b
S
MAX
400
300
300
400
0.9
50
t
HD;STA
kHz
ns
µ s
µ s
µ s
µ s
µ s
ns
µ s
µ s
ns
ns
pF
UNITS
Note 1
Note 2
Note 3
COMMENTS
t
SU;STO
Rev. 03/30/05
P
R
max)