LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 166

no-image

LPC47M192-NW

Manufacturer Part Number
LPC47M192-NW
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of LPC47M192-NW

Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC47M192-NW
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
LPC47M192-NW
Manufacturer:
SMSC
Quantity:
20 000
Company:
Part Number:
LPC47M192-NW
Quantity:
4 000
9
The Configuration of the LPC47M192 is very flexible and is based on the configuration architecture implemented in
typical Plug-and-Play components. The LPC47M192 is designed for motherboard applications in which the resources
required by their components are known. With its flexible resource allocation architecture, the LPC47M192 allows
the BIOS to assign resources at POST.
9.1 System Elements
9.1.1 PRIMARY CONFIGURATION ADDRESS DECODER
After a hard reset (PCI_RESET# pin asserted) or Vcc Power On Reset the LPC47M192 is in the Run Mode with all
logical devices disabled. The logical devices may be configured through two standard Configuration I/O Ports
(INDEX and DATA) by placing the LPC47M192 into Configuration Mode.
The BIOS uses these configuration ports to initialize the logical devices at POST. The INDEX and DATA ports are
only valid when the LPC47M192 is in Configuration Mode.
The SYSOPT pin is latched on the falling edge of the PCI_RESET# or on Vcc Power On Reset to determine the
configuration register’s base address. The SYSOPT pin is used to select the CONFIG PORT’s I/O address at power-
up. Once powered up the configuration port base address can be changed through configuration registers CR26 and
CR27. The SYSOPT pin is a hardware configuration pin which is shared with the GP24 signal on pin 45.
Note : An external pull-down resistor is required for the base IO address to be 0x02E for configuration. An external
pull-up resistor is required to move the base IO address for configuration to 0x04E.
The INDEX and DATA ports are effective only when the chip is in the Configuration State.
Note : The configuration port base address can be relocated through CR26 and CR27.
9.1.1.1
The device enters the Configuration State when the following Config Key is successfully written to the CONFIG
PORT.
9.1.1.2
The device exits the Configuration State when the following Config Key is successfully written to the CONFIG PORT.
SMSC DS – LPC47M192
CONFIGURATION
Entering the Configuration State
Exiting the Configuration State
CONFIG PORT (Note)
INDEX PORT (Note)
DATA PORT
PORT NAME
0x02E
0x02E
INDEX PORT + 1
10k PULL-DOWN
DATASHEET
SYSOPT= 0
RESISTOR
Config Key = <0x55>
Config Key = <0xAA>
Page 166
0x04E
0x04E
10K PULL-UP
SYSOPT= 1
RESISTOR
Write
Read/Write
Read/Write
TYPE
Rev. 03/30/05

Related parts for LPC47M192-NW