LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 68

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

LINE CONTROL REGISTER (LCR)
Address Offset = 3H, DLAB = 0, READ/WRITE
This register contains the format information of the serial line. The bit definitions are:
Bits 0 and 1
These two bits specify the number of bits in each transmitted or received serial character. The encoding of bits 0 and
1 is as follows:
The Start, Stop and Parity bits are not included in the word length.
Bit 2
This bit specifies the number of stop bits in each transmitted or received serial character. The following table
summarizes the information.
Note: The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting.
Bit 3
Parity Enable bit. When bit 3 is a logic “1”, a parity bit is generated (transmit data) or checked (receive data) between
the last data word bit and the first stop bit of the serial data. (The parity bit is used to generate an even or odd number
of 1s when the data word bits and the parity bit are summed).
SMSC DS – LPC47M192
MODE
ONLY
BIT 3
FIFO
0
0
BIT 2
IDENTIFICATION
0
0
INTERRUPT
REGISTER
BIT 1
1
0
BIT 0
0
0
BIT 2
0
1
1
1
1
BIT 1
Y LEVEL
0
0
1
1
PRIORIT
Fourth
Third
WORD LENGTH
Start LSB Data 5-8 bits MSB Parity
DATASHEET
BIT 0
5 bits
6 bits
7 bits
8 bits
0
1
0
1
--
Serial Data
INTERRUPT SET AND RESET FUNCTIONS
INTERRUPT
Page 68
Transmitter
MODEM
Register
Holding
Empty
Status
TYPE
WORD LENGTH
NUMBER OF
5 Bits
6 Bits
7 Bits
8 Bits
STOP BITS
1.5
Holding Register
or Ring Indicator
Clear to Send or
1
2
2
2
Data Set Ready
Stop
or Data Carrier
INTERRUPT
Transmitter
SOURCE
Empty
Detect
Holding Register
Reading the IIR
MODEM Status
INTERRUPT
Reading the
Interrupt) or
Transmitter
CONTROL
Register (if
Writing the
Source of
Register
RESET
Rev. 03/30/05