LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 30

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

7.3.9.2
7.3.9.3
7.3.9.4
7.3.9.5
7.3.9.6
7.3.10 LPC TRANSFERS
7.3.10.1
7.3.10.1.1
7.3.10.1.2
SMSC DS – LPC47M192
When PCI_RESET# goes inactive (high), the clock is assumed to have been running for 100usec prior to the
removal of the reset signal, so that everything is stable. This is the same reset active time after clock is stable
that is used for the PCI bus.
When PCI_RESET# goes active (low):
the host drives the LFRAME# signal high, tristates the LAD[3:0] signals, and ignores the LDRQ# signal.
the LPC47M192 must ignore LFRAME#, tristate the LAD[3:0] pins and drive the LDRQ# signal inactive (high).
SYNC Timeout
The SYNC value is driven within 3 clocks. If the host observes 3 consecutive clocks without a valid SYNC
pattern, it will abort the cycle.
The LPC47M192 does not assume any particular timeout. When the host is driving SYNC, it may have to
insert a very large number of wait states, depending on PCI latencies and retries.
SYNC Patterns and Maximum Number of SYNCS
If the SYNC pattern is 0101, then the host assumes that the maximum number of SYNCs is 8.
If the SYNC pattern is 0110, then no maximum number of SYNCs is assumed. The LPC47M192 has
protection mechanisms to complete the cycle. This is used for EPP data transfers and should utilize the
same timeout protection that is in EPP.
SYNC Error Indication
The LPC47M192 reports errors via the LAD[3:0] = 1010 SYNC encoding.
If the host was reading data from the LPC47M192, data will still be transferred in the next two nibbles.
This data may be invalid, but it will be transferred by the LPC47M192. If the host was writing data to the
LPC47M192, the data had already been transferred.
In the case of multiple byte cycles, such as memory and DMA cycles, an error SYNC terminates the cycle.
Therefore, if the host is transferring 4 bytes from a device, if the device returns the error SYNC in the first
byte, the other three bytes will not be transferred.
I/O and DMA START Fields
I/O and DMA cycles use a START field of 0000.
Reset Policy
The following rules govern the reset policy:
Wait State Requirements
I/O Transfers
The LPC47M192 inserts three wait states for an I/O read and two wait states for an I/O write cycle. A
SYNC of 0110 is used for all I/O transfers. The exception to this is for transfers where IOCHRDY would
normally be deasserted in an ISA transfer (i.e., EPP or IrCC transfers) in which case the sync pattern of
0110 is used and a large number of syncs may be inserted (up to 330 which corresponds to a timeout of
10us).
DMA Transfers
The LPC47M192 inserts three wait states for a DMA read and four wait states for a DMA write cycle. A
SYNC of 0101 is used for all DMA transfers.
See the example timing for the LPC cycles in the “Timing Diagrams” section.
DATASHEET
Page 30
Rev. 03/30/05