LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 165

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

User Note: When selecting an alternate function for a GPIO pin, all bits in the GPIO register must be properly
programmed, including in/out, polarity and output type. The polarity bit does not affect the DDRC function or the
either edge triggered interrupt functions.
User Note 1: If this pin is used for Ring Indicator wakeup, either the nRI2 event can be enabled via bit 1 in the
PME_EN1 register or the GP50 PME event can be enabled via bit 0 in the PME_EN5 register.
User Note 2: In order to use the P12, P16 and P17 functions, the corresponding GPIO must be programmed for
output, non-invert, and push-pull output type.
Note 1: If the EETI function is selected for this GPIO then both a high-to-low and a low-to-high edge will set the PME,
SMI and MSC status bits.
Note 2: The IRTX2 function can be used on this pin if the IR Location Mux bit in the Serial Port 2 IR Option register is
set.
Note 3: These pins default to an output and LOW on VCC POR and PCI Reset.
Note 4: If the FDC function is selected on this pin (nMTR1, nDS1, DRVDEN0, DRVDEN1) then bit 6 of the FDD
Mode Register (Configuration Register 0xF0 in Logical Device 0) will override bit 7 in the GPIO Control Register. Bit
7 of the FDD Mode Register will also affect the pin if the FDC function is selected.
Note 5: The nIO_SMI pin is inactive when the internal group SMI signal is inactive and when the SMI enable bit
(EN_SMI, bit 7 of the SMI_EN2 register) is ‘0’. When the output buffer type is OD, nIO_SMI pin is floating when
inactive; when the output buffer type is push-pull, the nIO_SMI pin is high when inactive.
Note 6: Bits 2 and 3 of the PME_STS4 and SMI_STS4 registers, and bit 3 of the PME_STS5 register may be set on
a VCC POR. If GP32, GP33 and GP53 are configured as input, then their corresponding PME and SMI status bits
will be set on a VCC POR. These GPIOs cannot be used for PME wakeup when the part is under VTR power
(VCC=0).
Note 7: These bits are R/W but have no effect on circuit operation.
SMSC DS – LPC47M192
Fan2
Register
Default = 0x00
LED1
Default = 0x00
LED2
Default = 0x00
Keyboard
Code
Default = 0x00
N/A
on VTR POR
on VTR POR
on VTR POR
on VTR POR
NAME
Preload
Scan
REG OFFSET
(R/W)
(R/W)
(R/W)
(R/W)
60-7F
(hex)
5C
5D
(R)
5E
5F
DATASHEET
Fan Preload Register 2
Bit[7:0] The FAN2 tachometer preload. This is the initial
value used in the computation of the FAN2 count.
Writing this register resets the tachometer count.
LED1
Bit[1:0] LED1 Control
00=off
01=blink at 1Hz rate with a 50% duty cycle (0.5 sec on,
0.5 sec off)
10=Blink at ½ HZ rate with a 25% duty cycle (0.5 sec on,
1.5 sec off)
11=on
Bits[7:2] Reserved
LED2
Bit[1:0] LED2 Control
00=off
01=blink at 1Hz rate with a 50% duty cycle (0.5 sec on,
0.5 sec off)
10=Blink at ½ HZ rate with a 25% duty cycle (0.5 sec on,
1.5 sec off)
11=on
Bits[7:2] Reserved
Keyboard Scan Code
Bit[0] LSB of Scan Code
Bit[7] MSB of Scan Code
Bits[7:0] Reserved – reads return 0
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Page 165
DESCRIPTION
Rev. 03/30/05