SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 106

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Coprocessor Interface
4.1
4-2
About coprocessors
The ARM7TDMI core instruction set enables you to implement specialized additional
instructions using coprocessors to extend functionality. These are separate processing
units that are tightly coupled to the ARM7TDMI processor. A typical coprocessor
contains:
•
•
•
•
•
A coprocessor is connected to the same data bus as the ARM7TDMI processor in the
system, and tracks the pipeline in the ARM7TDMI processor. This means that the
coprocessor can decode the instructions in the instruction stream, and execute those that
it supports. Each instruction progresses down both the ARM7TDMI core pipeline and
the coprocessor pipeline at the same time.
The execution of instructions is shared between the ARM7TDMI core and the
coprocessor.
The ARM7TDMI processor:
1.
2.
3.
The coprocessor:
1.
2.
3.
4.
If a coprocessor cannot execute an instruction, the instruction takes the undefined
instruction trap. You can choose whether to emulate coprocessor functions in software,
or to design a dedicated coprocessor.
an instruction pipeline (pipeline follower)
instruction decoding logic
handshake logic
a register bank
special processing logic, with its own data path.
Evaluates the instruction type and the condition codes to determine whether the
instructions are executed by the coprocessor, and communicates this to any
coprocessors in the system, using nCPI.
Generates any addresses that are required by the instruction, including
prefetching the next instruction to refill the pipeline.
Takes the undefined instruction trap if no coprocessor accepts the instruction.
Decodes instructions to determine whether it can accept the instruction.
Indicates whether it can accept the instruction by using CPA and CPB.
Fetches any values required from its own register bank.
Performs the operation required by the instruction.
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