SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 242

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug in Depth
B.8
B.8.1
B-24
Determining the core and system state
Determining the core state
When the ARM7TDMI core is in debug state, you examine the core and system state
by forcing the load and store multiples into the instruction pipeline.
Before you can examine the core and system state, the debugger must determine if the
processor entered debug from Thumb state or ARM state, by examining bit 4 of the
EmbeddedICE debug status register. When bit 4 is HIGH, the core has entered debug
from Thumb state, when bit 4 is LOW, the core has entered debug entered from ARM
state.
When the processor has entered debug state from Thumb state, the simplest course of
action is for the debugger to force the core back into ARM state. The debugger can then
execute the same sequence of instructions to determine the processor state.
To force the processor into ARM state while in debug, execute the following sequence
of Thumb instructions on the core:
Because all Thumb instructions are only 16 bits long, the simplest course of action,
when shifting scan chain 1, is to repeat the instruction. For example, the encoding for
to keep track of the half of the bus on which the processor expects to read the data.
You can use the sequences of ARM instructions in Example B-1 and Example B-2 on
page B-25 to determine the state of the processor.
With the processor in the ARM state, the instruction to execute is shown in
Example B-1.
is
Note
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, so when
Example B-1 Instruction to determine core state
shifts into scan chain 1, the debugger does not have
ARM DDI 0029G