SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 236

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug in Depth
B-18
•
The scan cells are not fully JTAG-compliant in that they do not have an update stage.
Therefore, while data is being moved around the scan chain, the contents of the scan cell
are not isolated from the output. From these operations, the output from the scan cell to
the core or to the external system can change on every scan clock. This does not affect
the ARM7TDMI core because its internal state does not change until it is clocked.
However, the rest of the system must be aware that every output can change
asynchronously as data is moved around the scan chain. External logic must ensure that
this does not harm the rest of the system.
Scan chain 0
Scan chain 0 is intended primarily for inter-device testing, EXTEST, and testing the
core, INTEST. Scan chain 0 is selected using the SCAN_N instruction as described at
SCAN_N (0010) on page B-10.
INTEST enables serial testing of the core. The TAP controller must be placed in
INTEST mode after scan chain 0 has been selected:
•
•
•
For a description of the core clocks during test and debug, see The ARM7TDMI core
clocks on page B-22.
EXTEST enables inter-device testing, useful for verifying the connections between
devices on a circuit board. The TAP controller must be placed in EXTEST mode after
scan chain 0 has been selected:
•
•
In SYSTEM mode, the scan cells are idle. System data is applied to inputs and
core outputs are applied to the system.
During CAPTURE-DR, the current outputs from the core logic are captured in the
output cells.
During SHIFT-DR, this captured data is shifted out while a new serial test pattern
is scanned in, therefore applying known stimuli to the inputs.
During RUN-TEST-IDLE, the core is clocked. Usually, the TAP controller only
spends one cycle in RUN-TEST-IDLE. The whole operation can then be repeated.
During CAPTURE-DR, the current inputs to the core logic from the system are
captured in the input cells.
During SHIFT-DR, this captured data is shifted out while a new serial test pattern
is scanned in, thus applying known values on the outputs of the core.
Note
Copyright © 1994-2001. All rights reserved.
ARM DDI 0029G