SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 56

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Programmer’s Model
2.6.2
2-10
System and User
r0
r1
r2
r3
r4
r5
r6
r7
SP
LR
PC
The Thumb-state register set
= banked register
CPSR
The Thumb-state register set is a subset of the ARM-state set. The programmer has
access to:
•
•
•
•
•
There are banked SPs, LRs, and SPSRs for each privileged mode. This register set is
shown in Figure 2-4.
SPSR_fiq
r0
r1
r2
r3
r4
r5
r6
r7
SP_fiq
LR_fiq
PC
Thumb-state general registers and program counter
CPSR
FIQ
8 general registers, r0–r7
the PC
the SP
the LR
the CPSR.
Thumb-state program status registers
Copyright © 1994-2001. All rights reserved.
Supervisor
SPSR_svc
r0
r1
r2
r3
r4
r5
r6
r7
SP_svc
LR_svc
PC
CPSR
Figure 2-4 Register organization in Thumb state
SPSR_abt
r0
r1
r2
r3
r4
r5
r6
r7
SP_abt
LR_abt
PC
CPSR
Abort
SPSR_irq
r0
r1
r2
r3
r4
r5
r6
r7
SP_irq
LR_irq
PC
CPSR
IRQ
ARM DDI 0029G
Undefined
SPSR_und
r0
r1
r2
r3
r4
r5
r6
r7
SP_und
LR_und
PC
CPSR