SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 61

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

2.7.3
ARM DDI 0029G
M[4:0]
10000
10001
10010
10011
10111
11011
11111
Reserved bits
Mode
User
FIQ
IRQ
Supervisor
Abort
Undefined
System
Mode bits
Bits M[4:0] determine the processor operating mode as shown in Table 2-2. Not all
combinations of the mode bits define a valid processor mode, so take care to use only
the bit combinations shown.
An illegal value programmed into M[4:0] causes the processor to enter an
unrecoverable state. If this occurs, apply reset.
The remaining bits in the PSRs are unused, but are reserved. When changing a PSR flag
or control bits, make sure that these reserved bits are not altered. Also, make sure that
your program does not rely on reserved bits containing specific values because future
processors might have these bits set to 1 or 0.
Visible Thumb-state registers
r0–r7, SP, LR, PC, CPSR
r0–r7, SP_fiq, LR_fiq, PC, CPSR, SPSR_fiq
r0–r7, SP_irq, LR_irq, PC, CPSR, SPSR_irq
r0–r7, SP_svc, LR_svc, PC, CPSR,
SPSR_svc
r0–r7, SP_abt, LR_abt, PC, CPSR,
SPSR_abt
r0–r7, SP_und, LR_und, PC, CPSR,
SPSR_und
r0–r7, SP, LR, PC, CPSR
Copyright © 1994-2001. All rights reserved.
Visible ARM-state registers
r0–r14, PC, CPSR
r0–r7, r8_fiq–r14_fiq, PC, CPSR,
SPSR_fiq
r0–r12, r13_irq, r14_irq, PC, CPSR,
SPSR_irq
r0–r12, r13_svc, r14_svc, PC, CPSR,
SPSR_svc
r0–r12, r13_abt, r14_abt, PC, CPSR,
SPSR_abt
r0–r12, r13_und, r14_und, PC, CPSR,
SPSR_und
r0–r14, PC, CPSR
Table 2-2 PSR mode bit values
Programmer’s Model
2-15