SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 69

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

2.9
2.9.1
2.9.2
ARM DDI 0029G
Interrupt latencies
Maximum interrupt latencies
Minimum interrupt latencies
The calculations for maximum and minimum latency are described in:
•
•
When FIQs are enabled, the worst-case latency for FIQ comprises a combination of:
•
•
•
•
The total latency is therefore 29 processor cycles, just over 0.7 microseconds in a
system that uses a continuous 40MHz processor clock. At the end of this time, the
ARM7TDMI processor executes the instruction at
The maximum IRQ latency calculation is similar, but must allow for the fact that FIQ,
having higher priority, can delay entry into the IRQ handling routine for an arbitrary
length of time.
The minimum latency for FIQ or IRQ is the shortest time the request can take through
the synchronizer, T
Maximum interrupt latencies on page 2-23
Minimum interrupt latencies on page 2-23.
The longest time the request can take to pass through the synchronizer, T
(four processor cycles).
The time for the longest instruction to complete, T
an LDM which loads all the registers including the PC. T
wait state system.
The time for the Data Abort entry, T
The time for FIQ entry, T
Copyright © 1994-2001. All rights reserved.
syncmin
, plus T
fiq
fiq
(two cycles).
, a total of five processor cycles.
exc
(three cycles).
.
ldm
. The longest instruction, is
ldm
is 20 cycles in a zero
Programmer’s Model
syncmax
2-23