SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 237

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI 0029G
•
During RUN-TEST-IDLE, the core is not clocked.
The operation can then be repeated.
Scan chain 1
The primary use for scan chain 1 is for debugging, although it can be used for EXTEST
on the data bus. Scan chain 1 is selected using the SCAN_N TAP controller instruction.
Debugging is similar to INTEST and the procedure described above for scan chain 0
must be followed.
Scan chain 1 is 33 bits long, 32 bits for the data value, plus the scan cell on the
BREAKPT core input. This 33rd bit serves four purposes:
1.
2.
3.
4.
Scan chain 2
Purpose
Length
During UPDATE-DR, the value shifted into the data bus D[31:0] scan cells
appears on the outputs. For all other outputs, the value appears as the data is
shifted round.
Under normal INTEST test conditions, it enables a known value to be scanned
into the BREAKPT input.
During EXTEST test conditions, the value applied to the BREAKPT input from
the system can be captured.
While debugging, the value placed in the 33rd bit determines if the ARM7TDMI
core synchronizes back to system speed before executing the instruction. See
System speed access on page B-31 for further details.
After the ARM7TDMI core has entered debug state, the first time this bit is
captured and scanned out, its value tells the debugger if the core entered debug
state due to a breakpoint, bit 33 clear, or a watchpoint, bit 33 set.
Note
Copyright © 1994-2001. All rights reserved.
Enables the EmbeddedICE macrocell registers to be accessed. The order
of the scan chain, from TDI to TDO is:
1.
2.
See EmbeddedICE block diagram on page B-41.
38 bits.
Read/write, register address bits 4 to 0.
Data value bits 31 to 0.
Debug in Depth
B-19