SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 231

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI 0029G
When the BYPASS instruction is loaded into the instruction register, all the scan cells
assume their normal system mode of operation. The BYPASS instruction has no effect
on the system pins:
•
•
•
All unused instruction codes default to the BYPASS instruction.
BYPASS does not enable the processor to exit debug state or synchronize to MCLK for
a system speed access while in debug state. You must use RESTART to achieve this.
In the CAPTURE-DR state, a logic 0 is captured the bypass register.
In the SHIFT-DR state, test data is shifted into the bypass register through TDI
and shifted out through TDO after a delay of one TCK cycle. The first bit to shift
out is a zero.
In the UPDATE-DR state, the bypass register is not affected.
Note
Copyright © 1994-2001. All rights reserved.
Debug in Depth
B-13